Software pipelining on a network on chip

• US 8,261,025 B2
• Filed: 11/12/2007
• Issued: 09/04/2012
• Est. Priority Date: 11/12/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mejdrich, Eric O., Schardt, Paul E., Shearer, Robert A.
• Primary Examiner(s): Chan, Eddie P
• Assistant Examiner(s): Giroux, George
• Application Number:
  US11/938,376
• Publication Number:
  US 20090125574A1
• Time in Patent Office: 1,758 Days
• Field of Search: None
• US Class Current: 711/147
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/252 Store and forward routing
• CPC Class Codes: H04L 49/3036 Shared queuing
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.

Claims

1. A method of sharing memory in a software pipeline, the method implemented on a network on chip (‘

NOC’

), the NOC comprising integrated processor (‘

IP’

) blocks, routers, memory communications controllers, and network interface controllers, each IP block operatively coupled to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the method comprising;

segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage executing in a thread of execution on an IP block; and

allocating, by at least one of the stages, memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated, wherein data elements for determining when the shared memory can be deallocated further comprise a table comprising at least one row for each path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is in use by a stage in a path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is no longer required for use by a stage in the path of execution in the pipeline;

determining, by at least one stage in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and

deallocating the shared memory.

2. The method of claim 1 wherein segmenting a computer software application into stages of a software pipeline further comprises authorizing two or more stages to change values of the data elements for determining when the shared memory can be deallocated.

3. The method of claim 1 wherein:

segmenting a computer software application into stages of a software pipeline further comprises authorizing at least one stage to determine that the shared memory can be deallocated; and

determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by the at least one authorized stage, that the shared memory can be deallocated.

4. The method of claim 1 wherein determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by a designated stage in dependence upon data values in the columns of the table, that the shared memory can be deallocated.

5. The method of claim 1 wherein determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by a designated stage, that data values in the data elements for determining when the shared memory can be deallocated in each row of the table are equal.

6. A network on chip (‘

NOC’

) for sharing memory in a software pipeline, the NOC comprising integrated processor (‘

IP’

) blocks, routers, memory communications controllers, and network interface controllers, each IP block operatively coupled to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC further comprising;

a computer software application segmented into stages as the software pipeline, the software pipeline comprising one or more paths of execution, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID and executing on a thread of execution on an IP block; and

memory allocated by at least one of the stages to be shared among at least two stages, including a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated, wherein data elements for determining when the shared memory can be deallocated further comprise a table comprising at least one row for each path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is in use by a stage in a path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is no longer required for use by a stage in the path of execution in the pipeline.

7. The NOC of claim 6 wherein the computer software application segmented into stages of a software pipeline further comprises two or more stages authorized to change values of the data elements for determining when the shared memory can be deallocated.

8. The NOC of claim 6 wherein:

the computer software application segmented into stages of a software pipeline further comprises at least one stage authorized to determine that the shared memory can be deallocated.

9. The NOC of claim 6 wherein one of the stages is designated responsible for determining, in dependence upon data values in the columns of the table, that the shared memory can be deallocated.

10. The NOC of claim 6 wherein one of the stages is designated responsible for determining, when data values in the data elements for determining when the shared memory can be deallocated in each row of the table are equal, that the shared memory can be deallocated.

11. A computer program product for sharing memory in a software pipeline on a network on chip (‘

NOC’

), the NOC comprising integrated processor (‘

IP’

) blocks, routers, memory communications controllers, and network interface controllers, each IP block operatively coupled to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the computer program product including computer program instructions disposed in a recordable computer readable medium, the computer program instructions capable of;

segmenting a computer software application into stages of a software pipeline, the pipeline comprising one or more paths of execution, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID; and

allocating, by at least one of the stages, memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated, wherein the data elements for determining when the shared memory can be deallocated further comprise a table comprising at least one row for each path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is in use by a stage in a path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is no longer required for use by a stage in the path of execution in the pipeline;

executing each stage on a thread of execution on an IP block;

determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated; and

deallocating the shared memory.

12. The computer program product of claim 11 wherein segmenting a computer software application into stages of a software pipeline further comprises authorizing two or more stages to change values of the data elements for determining when the shared memory can be deallocated.

13. The computer program product of claim 11 wherein:

segmenting a computer software application into stages of a software pipeline further comprises authorizing at least one stage to determine that the shared memory can be deallocated; and

determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by the at least one authorized stage, that the shared memory can be deallocated.

14. The computer program product of claim 11 wherein determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by a designated stage in dependence upon data values in the columns of the table, that the shared memory can be deallocated.

15. The computer program product of claim 11 wherein determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by a designated stage, that data values in the data elements for determining when the shared memory can be deallocated in each row of the table are equal.