Memory management device for accessing cache memory or main memory
First Claim
1. A memory management device comprising:
- a first memory management unit converting a logical address for accessing a cache memory into a physical address for accessing the cache memory, and included in a processor;
a cache controller accessing the cache memory based on the physical address for accessing the cache memory, and included in the processor;
an access history storage storing access history data indicating an access state to a main memory outside the processor, and included in the processor, wherein the access history includes a rewrite frequency for each location in the main memory;
an address relation storage storing address relation data indicating a relationship between a logical address and a physical address in the main memory, and included in the processor; and
a second memory management unit converting a logical address for accessing the main memory into a physical address for accessing the main memory based on the access history data and the address relation data, and accessing the main memory based on the physical address for accessing the main memory, and further, included in the processor.
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Accused Products
Abstract
An example of a device comprises a first MMU converting a logical address into a physical address for a cache, a controller accessing the cache based on the physical address for the cache, a first storage storing history data showing an access state to a main memory outside a processor, a second storage storing relation data showing a relationship between a logical address and a physical address in the main memory, and a second MMU converting a logical address into a physical address for the main memory based on the history and relation data and accessing the main memory based on the physical address for the main memory. The first and second MMU, controller, first storage, second storage are included in the processor.
87 Citations
19 Claims
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1. A memory management device comprising:
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a first memory management unit converting a logical address for accessing a cache memory into a physical address for accessing the cache memory, and included in a processor; a cache controller accessing the cache memory based on the physical address for accessing the cache memory, and included in the processor; an access history storage storing access history data indicating an access state to a main memory outside the processor, and included in the processor, wherein the access history includes a rewrite frequency for each location in the main memory; an address relation storage storing address relation data indicating a relationship between a logical address and a physical address in the main memory, and included in the processor; and a second memory management unit converting a logical address for accessing the main memory into a physical address for accessing the main memory based on the access history data and the address relation data, and accessing the main memory based on the physical address for accessing the main memory, and further, included in the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A memory management device comprising:
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a first memory management unit converting a logical address for accessing a cache memory into a physical address for accessing the cache memory, and included in a processor; an access history storage storing access history data indicating an access state to a main memory outside the processor, and included in the processor, wherein the access history includes a rewrite frequency for each location in the main memory; an address relation storage storing address relation data indicating_a relationship between a logical address and a physical address in the main memory, and included in the processor; a second memory management unit converting a logical address for accessing the main memory into a physical address for accessing the main memory based on the access history data and the address relation data, and included in the processor; and a controller accessing the cache memory based on a physical address for accessing the cache memory, and accessing the main memory based on a physical address for accessing the main memory, and included in the processor. - View Dependent Claims (16, 17, 18, 19)
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Specification