Apparatus, system, and method for using multi-level cell solid-state storage as single level cell solid-state storage
First Claim
1. A method to store information in a storage device comprising one or more multi-level memory cells, the method comprising:
- reading a data bit in a multi-level memory cell in a first read operation;
reading an audit bit in the multi-level memory cell in a second read operation separate from the first read operation;
determining that the audit bit fails to match an expected value for the audit bit; and
determining that a validity of the data bit is suspect in response to the audit bit failing to match an expected value of the audit bit.
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Accused Products
Abstract
An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.
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Citations
25 Claims
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1. A method to store information in a storage device comprising one or more multi-level memory cells, the method comprising:
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reading a data bit in a multi-level memory cell in a first read operation; reading an audit bit in the multi-level memory cell in a second read operation separate from the first read operation; determining that the audit bit fails to match an expected value for the audit bit; and determining that a validity of the data bit is suspect in response to the audit bit failing to match an expected value of the audit bit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An apparatus to store information in a storage device comprising one or more multi-level memory cells, the apparatus comprising instructions to execute the following:
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receiving a write command from a client, the write command comprising a logical block address; mapping the logical block address received from the client to one or more page pairs of the storage device, wherein each page pair comprises a lower page associated with a least significant bit (LSB) of a plurality of multi-level cells in the storage device, and an upper page associated with a most significant bit (MSB) of the multi-level cells; setting a physical address for storing data associated with the write command to the physical address for the lower pages of the one or more page pairs; and writing data associated with the write command received from the client to only one of the pages in each page pair of the one or more page pairs. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A system for storing information in a storage device comprising one or more multi-level memory cells, the system comprising:
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a driver configured to receive a write command from a client, the write command comprising a logical block address; a mapping logic module configured to map the logical block address received from the client to one or more page pairs of the storage device, wherein each page pair comprises a lower page associated with a least significant bit (LSB) of a plurality of multi-level cells in the storage device, and an upper page associated with a most significant bit (MSB) of the multi-level cells; the mapping logic further configured to set a physical address for storing data associated with the write command to the physical address for the lower pages of the page pair; and a hardware controller configured to write data associated with the write command received from the client to the physical address supplied by the mapping logic module. - View Dependent Claims (23, 24, 25)
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Specification