Data scrambling schemes for memory devices

• US 8,261,159 B1
• Filed: 10/28/2009
• Issued: 09/04/2012
• Est. Priority Date: 10/30/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Sommer, Naftali, Anholt, Micha, Golov, Oren, Perlmutter, Uri, Winter, Shai, Semo, Gil
• Primary Examiner(s): Duncan, Marc
• Application Number:
  US12/607,085
• Time in Patent Office: 1,042 Days
• Field of Search: 714/768, 714/773, 713/193
• US Class Current: 714/768
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

A method for data storage includes defining a set of scrambling sequences, each sequence including bits in respective bit positions having bit values, such that a distribution of the bit values in any give bit position satisfies a predefined statistical criterion. Each data word is scrambled using a respective scrambling sequence selected from the set. The scrambled data words are stored in the memory device.

Claims

1. A method for data storage, comprising:

defining a set of scrambling sequences, each sequence comprising bits in respective bit positions having bit values, such that a distribution of the bit values in any give bit position satisfies a predefined statistical criterion;

scrambling each data word using a respective scrambling sequence selected from the set; and

storing the scrambled data words in the memory device,

wherein defining the set comprises specifying the set to include a group of the scrambling sequences, and respective inverses of the scrambling sequences in the group.

2. The method according to claim 1, wherein the statistical criterion specifies that half of the bit values in any given bit position are “

0” and

the other half of the bit values are “

1”

.

3. The method according to claim 1, wherein specifying the set comprises:

defining a scrambling seed comprising multiple bits, each combination of values of the bits defining a respective scrambling sequence;

adding to the scrambling seed an additional bit, which selects between the respective scrambling sequence and an inverse of the respective scrambling sequence; and

generating the scrambling sequences in the set using the scrambling seed, including the additional bit.

4. A method for data storage, comprising:

encoding data for storage in a memory device using an Error Correction Code (ECC) so as to produce ECC-encoded data;

encoding a scrambling sequence with the ECC so as to produce an ECC-encoded scrambling sequence;

calculating a bit-wise Exclusive Or (XOR) between the ECC-encoded data and the ECC-encoded scrambling sequence so as to produce a result; and

storing the result in the memory device.

5. The method according to claim 4, wherein encoding the scrambling sequence comprises:

scrambling the data using two or more candidate scrambling sequences, so as to produce respective scrambled data sequences;

selecting one of the scrambling sequences based on a condition defined over the scrambled data sequences; and

encoding the selected scrambling sequence to produce the ECC-encoded scrambling sequence.

6. The method according to claim 5, wherein scrambling the data and selecting the scrambling sequence are performed at least partly in parallel to encoding the data with the ECC.

7. Apparatus for data storage, comprising:

an interface, which is configured to communicate with a memory device; and

a processor, which is configured to define a set of scrambling sequences, each sequence comprising bits in respective bit positions having bit values, such that a distribution of the bit values in any give bit position satisfies a predefined statistical criterion, to scramble each data word using a respective scrambling sequence selected from the set, and to store the scrambled data words in the memory device,

wherein the processor is configured to specify the set to include a group of the scrambling sequences, and respective inverses of the scrambling sequences in the group.

8. The apparatus according to claim 7, wherein the statistical criterion specifies that half of the bit values in any given bit position are “

0” and

the other half of the bit values are “

1”

.

9. The apparatus according to claim 7, wherein the processor is configured to specify the set by:

defining a scrambling seed comprising multiple bits, each combination of values of the bits defining a respective scrambling sequence;

adding to the scrambling seed an additional bit, which selects between the respective scrambling sequence and an inverse of the respective scrambling sequence; and

generating the scrambling sequences in the set using the scrambling seed, including the additional bit.

10. Apparatus for data storage, comprising:

an interface, which is configured to communicate with a memory device; and

a processor, which is configured to encode data for storage in the memory device using an Error Correction Code (ECC) so as to produce ECC-encoded data, to encode a scrambling sequence with the ECC so as to produce an ECC-encoded scrambling sequence, to calculate a bit-wise Exclusive Or (XOR) between the ECC-encoded data and the ECC-encoded scrambling sequence so as to produce a result, and to store the result in the memory device.

11. The apparatus according to claim 10, wherein the processor is configured to scramble the data using two or more candidate scrambling sequences so as to produce respective scrambled data sequences, to select one of the scrambling sequences based on a condition defined over the scrambled data sequences, and to encode the selected scrambling sequence so as to produce the ECC-encoded scrambling sequence.

12. The apparatus according to claim 11, wherein the processor is configured to scramble the data and select the scrambling sequence at least partly in parallel to encoding the data with the ECC.