Micro piezoresistive pressure sensor and manufacturing method thereof

• US 8,261,617 B2
• Filed: 04/21/2008
• Issued: 09/11/2012
• Est. Priority Date: 12/05/2007
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Choi, Chang Auck, Je, Chang Han, Hwang, Gunn, Kim, Youn Tae, Jung, Sung Hae, Lee, Myung Lae, Lee, Sung Sik, Moon, Seok Hwan
• Primary Examiner(s): ALLEN, ANDRE J
• Application Number:
  US12/745,745
• Publication Number:
  US 20100251826A1
• Time in Patent Office: 1,604 Days
• Field of Search: 73700-756
• US Class Current: 73/721
• CPC Class Codes: B81C 1/00047 Cavities
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: Y10T 29/42 Piezoelectric device making
• CPC Class Codes: Y10T 29/49 Method of mechanical manufacture

Abstract

A micro semiconductor-type pressure sensor and a manufacturing method thereof are provided. The micro semi-conductor-type pressure sensor is implemented by etching a cavity-formation region of a substrate to form a plurality of trenches, oxidizing the plurality of trenches through a thermal oxidation process to form a cavity-formation oxide layer, forming a membrane-formation material layer on upper portions of the cavity-formation oxide layer and the substrate, forming a plurality of etching holes in the membrane-formation material layer, removing the cavity-formation oxide layer through the plurality of etching holes to form a cavity buried in the substrate, forming a membrane reinforcing layer on an upper portion of the membrane-formation material layer to form a membrane for closing the cavity, and forming sensitive films made of a piezoresisive material on an upper portion of the membrane.

Claims

1. A micro piezoresistive pressure sensor comprising:

a silicon substrate;

a cavity formed in a sensor region of the silicon substrate;

a membrane formed over the silicon substrate and configured to substantially enclose the cavity;

a sensitive film, including piezoresistive material, formed over the membrane; and

one or more semiconductor integrated devices which are formed in a device region of the silicon substrate,

wherein the semiconductor integrated devices are complementary metal oxide semiconductor (CMOS) devices,

wherein the membrane is coupled to the substrate in a CMOS process other than a bonding method, and

wherein the membrane is coupled to the sensitive film in a CMOS process other than a bonding method.

2. The micro piezoresistive pressure sensor of claim 1, wherein the cavity and the membrane are formed together at substantially the same time by using a CMOS device manufacturing process for manufacturing the semiconductor integrated devices.

3. The micro piezoresistive pressure sensor of claim 2, wherein the cavity in the sensor region is formed by performing a CMOS process, the CMOS process including forming a trench in the silicon substrate, forming an oxide layer in the trench, and removing the oxide layer in the trench.

4. The micro piezoresistive pressure sensor of claim 2,

wherein the membrane comprises a laminated insulating layer, and

wherein the laminated insulating layer includes (i) a polysilicon layer, and (ii) any of a silicon nitride layer and a silicon oxide layer.

5. The micro piezoresistive pressure sensor of claim 4, wherein the membrane is formed using a CMOS process including a diffusing thermal treatment process and a silicon oxide layer forming process.

6. A method of manufacturing a micro piezoresistive pressure sensor, comprising:

forming a trench by etching a sensor region of a substrate;

forming a first oxide layer to fill the trench;

forming a first membrane layer over the first oxide layer and the substrate;

forming a plurality of etching holes in the first membrane layer;

removing the first oxide layer through the plurality of etching holes to form a cavity;

filling the etching holes to form a second membrane layer, the second membrane layer being disposed over the cavity and substantially enclosing the cavity; and

forming a piezoresistive film over the second membrane layer.

7. The method of claim 6, wherein the first membrane layer is coupled to the substrate using a CMOS process other than a bonding method, and

wherein the second membrane layer is coupled to the piezoresistive film using a CMOS process other than a bonding method.

8. The method of claim 7, the method further comprising forming a stress buffer layer in a device region of the substrate, before forming the trench.

9. The method of claim 8, the method further comprising:

forming semiconductor integrated devices in the device region of the substrate; and

forming a field oxide layer in the device region of the substrate,

wherein the semiconductor integrated devices are formed between neighboring field oxide layers in the device region.

10. The method of claim 9, wherein the first oxide layer in the sensor region and the field oxide layer in the device region are formed at substantially the same time using a thermal oxidation process.

11. The method of claim 10, wherein a width of the trench is 2 μ

m or less, and a width of an interval between neighboring trenches is 0.56 to 0.60 times the width of the trench.

12. The method of claim 9, the method further comprising removing the stress buffer layer formed in the device region through a wet etching process and performing a polishing process including a chemical mechanical polishing (CMP) process for surface planarization, after forming the first oxide layer and the field oxide layer.

13. The method of claim 12, the method further comprising forming a gate, a source, and a drain in the device region, after the step of removing the stress buffer layer.

14. The method of claim 12, the method further comprising filling the plurality of etching holes by performing thermal oxidation on the first membrane layer to form the second membrane layer.

15. The method of claim 14, wherein the first membrane layer is made of polysilicon.

16. The method of claim 15, wherein the step of removing the first oxide layer to form the cavity includes:

removing the first oxide layer using (i) an oxide-layer wet etching method employing a hydro fluoric solution, or (ii) an oxide-layer dry etching method utilizing an etch ratio difference between the polysilicon and the first oxide layer.

17. The method of claim 14, wherein the thermal oxidation of the first membrane layer in the sensor region is performed at substantially the same time as a diffusing thermal treatment process for the source and the drain in the device region.

18. The method of claim 17, wherein a diameter of the plurality of etching holes is in a range of 0.5 to 1.5 μ

m.

19. The method of claim 14, the method further comprising forming an insulating layer over the source, the drain, and the gate in the device region.

20. The method of claim 19, the method further comprising forming a membrane reinforcing layer over the second membrane layer,

wherein the step of forming the insulating layer in the device region and the step of forming the membrane reinforcing layer in the sensor region are performed at substantially the same time.

21. The method of claim 20, wherein each of the insulating layer and the membrane reinforcing layer are include a silicon oxide layer or a silicon nitride layer.

22. The method of claim 14, after the step of forming the insulating layer in the device region and forming the piezoresistive film, the method further comprising:

forming a chip-protection oxide layer over the insulating layer and the piezoresistive film;

opening a portion of the chip-protection oxide layer; and

forming metal layers configured to electrically couple the piezoresistive film and the semiconductor integrated devices.