Pixel structure and method for forming the same

• US 8,263,445 B2
• Filed: 01/05/2010
• Issued: 09/11/2012
• Est. Priority Date: 04/03/2007
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Ting, Yu-Hsin
• Primary Examiner(s): Pham, Long
• Application Number:
  US12/652,169
• Publication Number:
  US 20100112773A1
• Time in Patent Office: 980 Days
• Field of Search: 438/57, 438/155, 438/381
• US Class Current: 438/155
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors

Abstract

A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer.

Claims

1. A method for forming a pixel structure, the pixel structure having at least one transistor and a first storage capacitor electrically connected to the transistor, the method comprising:

forming a first conductive layer;

covering an interlayer dielectric layer having a first opening on the first conductive layer;

forming a second conductive layer on a part of the interlayer dielectric layer, the second conductive layer electrically connecting to the first conductive layer through the first opening;

covering a passivation layer having a second opening on the transistor and the second conductive layer;

forming a third conductive layer on a part of the passivation layer, the third conductive layer electrically connecting to the transistor through the second opening; and

covering a fourth conductive layer on the second conductive layer and a part of the interlayer dielectric layer,

wherein the first storage capacitor is formed by the third conductive layer, the passivation layer, the fourth conductive layer, and the second conductive layer.

2. The method according to claim 1, further comprising:

forming a semiconductor layer; and

covering an insulating layer having at least two third openings on the semiconductor layer.

3. The method according to claim 2, further comprising:

forming a second storage capacitor by the first conductive layer, the insulating layer and a part of the semiconductor layer.

4. The method according to claim 3, further comprising:

forming a third storage capacitor by the second conductive layer, the interlayer dielectric layer, the insulating layer and the part of the semiconductor layer.

5. The method according to claim 2, wherein the semiconductor layer comprises at least one doping region, at least one intrinsic region, or combinations thereof.

6. The method according to claim 1, wherein the first conductive layer, the second conductive layer and the fourth conductive layer have substantially identical potential.

7. The method according to claim 1, wherein potential of the first conductive layer, the second conductive layer and the fourth conductive layer is common potential.

8. The method according to claim 1, further comprising:

forming a semiconductor layer; and

covering an insulating layer having at least two third openings on the semiconductor layer.

9. The method according to claim 8, further comprising:

forming a second storage capacitor by the first conductive layer, the insulating layer and a part of the semiconductor layer.

10. The method according to claim 9, further comprising:

forming a third storage capacitor by the second conductive layer, the interlayer dielectric layer, the insulating layer and the part of the semiconductor layer.

11. The method according to claim 1, wherein the first conductive layer is connected to a common electrode line.