Dielectric punch-through stoppers for forming FinFETs having dual fin heights

• US 8,263,462 B2
• Filed: 12/31/2008
• Issued: 09/11/2012
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hung, Shih-Ting, Chang, Cheng-Hung, Lee, Chen-Yi, Yeh, Chen-Nan, Yu, Chen-Hua
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Fan, Michele
• Application Number:
  US12/347,123
• Publication Number:
  US 20100163971A1
• Time in Patent Office: 1,350 Days
• Field of Search: 257/288, 257/327, 257/497, 257/E29.112, 257/E29.255, 438/197, 438/286, 438/294
• US Class Current: 438/286
• CPC Class Codes: H01L 21/76202 using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO H01L21/76235 takes precedence; together with vertical isolation, e.g. LOCOS in a SOI substrate, H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate comprising a first portion and a second portion;

a first shallow trench isolation (STI) region and a second STI region, wherein the first STI region has a first top surface substantially level with a second top surface of the second STI region;

a first Fin field-effect transistor (FinFET) over the first portion of the semiconductor substrate, wherein the first FinFET comprises a first fin having a first fin height, wherein the first fin is adjacent to and above the first STI region;

a second FinFET over the second portion of the semiconductor substrate, wherein the second FinFET comprises a second fin having a second fin height different from the first fin height, wherein the second fin is adjacent to and above the second STI region, and wherein a first top surface of the first fin is substantially level with a second top surface of the second fin;

a punch-through stopper underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate, and wherein the punch-through stopper is formed of a dielectric material that is an oxidized portion of the first fin; and

an additional fin underlying and at least partially vertically overlapping the first fin, wherein the punch-through stopper electrically disconnects the additional fin from the first fin.

2. The semiconductor structure of claim 1, wherein a first bottom surface of the first STI region is substantially level with a second bottom surface of the second STI region.

3. The semiconductor structure of claim 1 further comprising an additional punch-through stopper underlying and adjoining the second fin, wherein the punch-through stopper and the additional punch-through stopper are not level with each other.

4. The semiconductor structure of claim 3 further comprising an additional fin directly underlying and adjoining the additional punch-through stopper, and wherein the additional fin and the second fin have substantially a same width.

5. The semiconductor structure of claim 1, wherein the punch-through stopper comprises an oxide of the semiconductor substrate.

6. The semiconductor structure of claim 1, wherein the first and the second fins are substantially above the first and the second STI regions, respectively, and wherein the first and the second fin heights are the heights measured from above the first and the second STI regions, respectively.

7. A semiconductor structure comprising:

a semiconductor substrate comprising a first portion and a second portion;

a first Fin field-effect transistor (FinFET) over the first portion of the semiconductor substrate, wherein the first FinFET comprises a first fin having a first fin height;

a second FinFET over the second portion of the semiconductor substrate, wherein the second FinFET comprises a second fin having a second fin height different from the first fin height, and wherein a first top surface of the first fin is substantially level with a second top surface of the second fin;

a first shallow trench isolation (STI) region adjacent the first fin, wherein the first fin is above the first STI region;

a second STI region adjacent the second fin, wherein the second fin is above the second STI region, and wherein the first STI region has a first top surface substantially level with a second top surface of the second STI region; and

a punch-through stopper underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate, and wherein the punch-through stopper is an oxidized portion of the first fin.

8. The semiconductor structure of claim 7, wherein a first bottom surface of the first STI region is substantially level with a second bottom surface of the second STI region.

9. The semiconductor structure of claim 7 further comprising an additional fin directly underlying the first fin, wherein the punch-through stopper electrically disconnects the additional fin from the first fin.

10. The semiconductor structure of claim 7 further comprising an additional punch-through stopper underlying and adjoining the second fin, wherein the punch-through stopper and the additional punch-through stopper are not level with each other.

11. The semiconductor structure of claim 7, wherein the first and the second fins are substantially above the first and the second STI regions, respectively, and wherein the first and the second fin heights are the heights measured from above the first and the second STI regions, respectively.