Thin film transistor and method of manufacturing the same

• US 8,263,978 B2
• Filed: 05/06/2009
• Issued: 09/11/2012
• Est. Priority Date: 09/24/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoo, Byung-wook, Lee, Sang-yoon, Ryu, Myung-kwan, Kim, Tae-sang, Kwon, Jang-yeon, Park, Kyung-bae, Son, Kyung-seok, Jung, Ji-sim
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US12/453,295
• Publication Number:
  US 20100072480A1
• Time in Patent Office: 1,224 Days
• Field of Search: 257/59, 257/72, 257/347, 257/E29.117, 257/E29.273
• US Class Current: 257/59
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02672 using crystallisation enhancing elements
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor (TFT) and a method of manufacturing the same are provided, the TFT including a gate insulating layer on a gate. A channel may be formed on a portion of the gate insulating layer corresponding to the gate. A metal material may be formed on a surface of the channel. The metal material crystallizes the channel. A source and a drain may contact side surfaces of the channel.

Claims

1. A thin film transistor (TFT), comprising:

a gate insulating layer on a gate;

a crystallized channel on a portion of the gate insulating layer corresponding to the gate;

a metal material on a surface of the channel, wherein the metal material crystallizes the channel; and

a source and a drain contacting side surfaces of the channel,

wherein the channel is formed of polysilicon, and

the metal material includes at least one selected from the group consisting of nickel (Ni), silver (Ag), gold (Au), palladium (Pd), cobalt (Co), copper (Cu), iron (Fe), aluminum (Al), chromium (Cr), platinum (Pt) and combinations thereof.

2. The TFT of claim 1, wherein the metal material is on the surface of the channel between the channel and the source and between the channel and the drain.

3. The TFT of claim 1, wherein the metal material is on a portion of the channel wherein the channel and the source overlap and on a portion of the channel wherein the channel and the drain overlap.

4. The TFT of claim 1, wherein the channel is over the gate.

5. The TFT of claim 1, wherein the metal material has a thickness of about 0.1-nm to 20-nm.

6. The TFT of claim 1, further comprising an intermediate layer between the channel and the source and between the channel and the drain, wherein the intermediate layer reduces contact resistance between the channel and the source and between the channel and the drain.