Wiring substrate and semiconductor device

• US 8,263,983 B2
• Filed: 10/27/2004
• Issued: 09/11/2012
• Est. Priority Date: 10/28/2003
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Maekawa, Shinji, Arai, Yasuyuki
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US10/973,986
• Publication Number:
  US 20050121675A1
• Time in Patent Office: 2,876 Days
• Field of Search: 257/72, 257/57, 257/59, 257/66, 257/347
• US Class Current: 257/72
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H05K 2201/0116 Porous, e.g. foam
• CPC Class Codes: H05K 2203/013 Inkjet printing, e.g. for printing insulating material or resist using ink-jet printing to form a conductive pattern H05K3/125
• CPC Class Codes: H05K 3/1208 Pretreatment of the circuit board, e.g. modifying wetting properties; Patterning by using affinity patterns providing shape patterns H05K3/1258; adhesion treatments H05K3/38
• CPC Class Codes: H05K 3/125 by ink-jet printing
• CPC Class Codes: H05K 3/38 Improvement of the adhesion between the insulating substrate and the metal
• CPC Class Codes: H05K 3/386 by the use of an organic polymeric bonding layer, e.g. adhesive

Abstract

The present invention provides a thin wiring pattern such as wiring formed by discharging a droplet. In the present invention, a porous (including microporous) substance is formed as a base film in forming pattern by using a droplet discharge method (also referred to as an ink-jetting method). One feature of a wiring substrate according to the present invention provides a porous film and a conductive layer thereon. One feature of a semiconductor device of the present invention provides a thin film transistor in which a gate electrode is formed by the conductive layer having the above-described structure.

Claims

1. A semiconductor device comprising:

a first conductive layer over an insulating substrate;

an insulating layer over the first conductive layer;

a porous film over the insulating layer, wherein the insulating layer and the porous film have an opening that reaches the first conductive layer; and

a second conductive layer on and in contact with the porous film, wherein said second conductive layer is connected to the first conductive layer through the opening,

wherein an outermost side end portion of the second conductive layer is aligned with a side end portion of the porous film, and

wherein an entire top surface of the porous film is overlapped with the second conductive layer.

2. The semiconductor device according to claim 1, wherein the porous film has pores;

wherein the second conductive layer is formed by a conductive material; and

wherein at least one pore is filled with the conductive material.

3. The semiconductor device according to claim 1, wherein the porous film comprises a material selected from the group consisting of an organic material, a porous material having a skeleton by a bond of silicon and oxygen, a porous organic resin material, and a porous silica material.

4. The semiconductor device according to claim 1, wherein at least one of the first conductive layer and the second conductive layer comprises one of Ag, Au, Cu, and indium tin oxide.

5. The semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of a camera, a personal digital assistant, a personal computer, a cellular phone, and a television set.

6. The semiconductor device according to claim 1, wherein the insulating layer is capable to flatten an irregularity caused by the first conductive layer.