Semiconductor device and manufacturing method thereof

• US 8,264,012 B2
• Filed: 10/20/2010
• Issued: 09/11/2012
• Est. Priority Date: 02/28/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Hara, Akito
• Primary Examiner(s): Tran, Tony
• Application Number:
  US12/908,231
• Publication Number:
  US 20110031540A1
• Time in Patent Office: 692 Days
• Field of Search: 257/213
• US Class Current: 257/213
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×10¹⁸ cm⁻³ to 5.0×10¹⁹ cm⁻³, or alternatively, the strain generating layer contains self-interstitial atoms and/or vacancies of 1.0×10¹⁸ cm⁻³ to 5.0×10¹⁹ cm⁻³. In the latter case, at least a portion of the self-interstitial atoms and/or the vacancies exist as a cluster.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a gate electrode formed over the semiconductor substrate;

a source extension region and a drain extension region having a first depth formed in the semiconductor substrate;

a source region and a drain region having a second depth greater than the first depth formed in the semiconductor substrate;

a first semiconductor layer including SiGe formed in the source region and a second semiconductor layer including SiGe formed in the drain region;

a first impurity region including at least one of oxygen and carbon located between the first semiconductor layer and the source extension region, and a second impurity region including at least one of oxygen and carbon located between the second semiconductor layer and the drain extension region;

wherein concentration of the oxygen or the carbon is 1.0×

10¹⁸ cm<sup>−

3</sup> to 5.0×

10¹⁹ cm<sup>−

3</sup>;

wherein the impurity region includes self-interstitial atoms and/or vacancies; and

wherein the impurity region is a conductive region.