Semiconductor device wherein a first insulated gate field effect transistor is connected in series with a second field effect transistor

• US 8,264,015 B2
• Filed: 04/03/2009
• Issued: 09/11/2012
• Est. Priority Date: 04/04/2008
• Status: Active Grant

• Current Assignee: Klas-Håkan Eklund
• Original Assignee: Klas-Håkan Eklund
• Inventors: Eklund, Klas-Håkan
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US12/667,088
• Publication Number:
  US 20100327330A1
• Time in Patent Office: 1,257 Days
• Field of Search: 257/262, 257/341, 257/342, 257/398, 257/399, 257/400, 257/401, 257/E29.012, 257/E29.013, 257/E29.014, 257/E29.278
• US Class Current: 257/262
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A semiconductor device in which a first insulated gate field effect transistor (1) is connected in series with a second field effect transistor, FET, (2), wherein the second field effect transistor (2) has a heavily doped source region (19A) which is electrically connected to a heavily doped drain contact region (191) of the first insulated gate field effect transistor, and further that the breakthrough voltage of the first insulated gate field effect transistor (1) is higher than the pinch voltage, Vp, of the second field effect transistor (2).

Claims

1. A semiconductor device, comprising:

a first insulated gate field effect transistor connected in series with a second field effect transistor

wherein the second field effect transistor has a heavily doped source contact region electrically connected to a heavily doped drain contact region of the first insulated gate field effect transistor, and

wherein the breakthrough voltage of the first insulated gate field effect transistor is higher than the pinch voltage of the second field effect transistor.

2. A device according to claim 1, wherein the second field effect transistor comprises several field effect transistors in parallel with a common heavily doped source contact region.

3. A device according to claim 1, wherein the width W of the first insulated gate field effect transistor is at least 2 times larger than the width W of the second field effect transistor.

4. A device according to claim 1, wherein the second field effect transistor is a junction field effect transistor, JFET.

5. A device according to claim 1, wherein the second field effect transistor is an insulated gate field effect transistor.

6. A device according to claim 1, wherein the second field effect transistor with modified drain contact region connected in series with the first insulated gate field effect transistor is an insulated gate bipolar transistor.

7. A device according to claim 1, wherein the first insulated gate field effect transistor and the second field effect transistor are arranged on different substrates.

8. A device according to claim 1, wherein the first insulated gate field effect transistor and the second field effect transistor are arranged on a common substrate.

9. A device according to claim 1, wherein the first insulated gate field effect transistor and the second field effect transistor are merged together, and that the drain contact region for the first insulated gate field effect transistor is the same as source contact region for the second transistor device.

10. A device according to claim 1, wherein both the first insulated gate field effect transistor and the second field effect transistor are incorporated in a surface region of the substrate.

11. A device according to claim 4, wherein the second field effect transistor comprises a number of Ntop and Ptop layers arranged vertically to make up channels and gates of paralleled junction field effect transistors with a common source region.

12. A device according to claim 4, wherein the second field effect transistor comprises a number of Ntop and Ptop layers arranged horizontally to make up channels and gates of paralleled junction field effect transistors with a common source region.

13. A semiconductor device, comprising:

a first insulated gate field effect transistor connected in series with a second field effect transistor

wherein the second field effect transistor has a heavily doped source contact region electrically connected to a heavily doped drain contact region of the first insulated gate field effect transistor,

wherein the breakthrough voltage of the first insulated gate field effect transistor is higher than the pinch voltage of the second field effect transistor, and

wherein the second field effect transistor is a combination of one or more junction field transistors and one or more insulated gate field transistors, all with a common source contact diffusion.

14. A semiconductor device, comprising:

a first insulated gate field effect transistor connected in series with a second field effect transistor

wherein the second field effect transistor has a heavily doped source contact region electrically connected to a heavily doped drain contact region of the first insulated gate field effect transistor,

wherein the breakthrough voltage of the first insulated gate field effect transistor is higher than the pinch voltage of the second field effect transistor,

wherein the second field effect transistor is a junction field effect transistor, JFET and,

wherein the second field effect transistor comprises a number of Ntop and Ptop layers arranged one of i) vertically vertically to make up channels and gates of paralleled junction field effect transistors with a common source region, and ii) horizontally to make up channels and gates of paralleled junction field effect transistors with a common source region.