Accumulation type FinFET, circuits and fabrication method thereof

• US 8,264,032 B2
• Filed: 04/09/2010
• Issued: 09/11/2012
• Est. Priority Date: 09/01/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Chih Chieh, Chang, Chih-Sheng, Wann, Clement Hsingjen
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US12/757,271
• Publication Number:
  US 20110049613A1
• Time in Patent Office: 886 Days
• Field of Search: 257/327, 257/E29.255, 257/E27.06, 257/E21.409, 438/197
• US Class Current: 257/327
• CPC Class Codes: H01L 2029/7857 of the accumulation type
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer.

Claims

1. A FinFET, comprising:

a substrate;

a fin structure on the substrate, the fin structure including a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor, and the channel has a dopant concentration between about 1e18 cm<sup>−

3</sup> and about 3e18 cm<sup>−

3</sup>;

a gate dielectric layer over the channel; and

a gate over the gate dielectric layer.

2. The FinFET of claim 1, further comprising a well region that has a second type dopant below the source, the drain, and the channel.

3. The FinFET of claim 1, wherein the gate is capable of receiving a voltage, and the voltage is capable of shifting a Fermi-level of the channel toward a middle of a bandgap of the channel.

4. The FinFET of claim 1, wherein a width of the fin structure is about 30 nm or less.

5. The FinFET of claim 1, wherein the FinFET is an N-type FinFET and at least one of the source and the drain comprises at least one of Ge, SiGe, or Si.

6. The FinFET of claim 1, wherein the FinFET is a P-type FinFET and at least one of the source and the drain comprises at least one of a Ge, GeSn, SiGeSn or III-V semiconductor.

7. The FinFET of claim 1, further comprising:

a silicide layer formed over at least one of the source or the drain.

8. A method for forming a FinFET, comprising:

forming a fin structure on a substrate, the fin structure including a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor, and the channel has a dopant concentration between about 1e18 cm<sup>−

3</sup> and about 3e18 cm<sup>−

3</sup>;

forming a gate dielectric layer over the channel; and

forming a gate over the gate dielectric layer.

9. The method of claim 8, further comprising forming a well region below the source, the drain, and the channel, wherein the well region has a second type dopant.

10. The method of claim 8, wherein the gate is capable of receiving a voltage, and the voltage is capable of shifting a Fermi-level of the channel toward a half of a bandgap of the channel.

11. The method of claim 8, wherein forming the fin structure comprises defining a width of the channel and the width of channel is about 30 nm or less.

12. The method of claim 8, wherein the FinFET is a N-type FinFET and at least one of the source and the drain comprises Ge, SiGe, or Si.

13. The method of claim 8, wherein the FinFET is a P-type FinFET and at least one of the source and the drain comprises Ge, GeSn, SiGeSn or III-V semiconductor.

14. The method of claim 8, further comprising:

forming a silicide layer over at least one of the source or the drain.

15. An integrated circuit, comprising:

a substrate;

a dummy pattern including at least one of a first fin structure on the substrate, the first fin structure comprising a first channel between a first source and a first drain, wherein the first source, the first drain, and the first channel have a first type dopant; and

a FinFET over the substrate, the FinFET including;

a second fin structure on the substrate, the second fin structure including a second channel between a second source and a second drain, wherein the second source, the second drain, and the second channel have the first type dopant, and the second channel comprises at least one of a Ge, SiGe, or III-V semiconductor, and wherein at least one of the second source and the second drain comprises at least one of a Ge, SiGe, Si, GeSn, SiGeSn, or III-V semiconductor;

a gate dielectric layer over the second channel; and

a gate over the gate dielectric layer.

16. The integrated circuit of claim 15, wherein the FinFET further including a well region that has a second type dopant below the second source, the second drain, and the second channel.

17. The integrated circuit of claim 15, wherein the second channel has a dopant concentration between about 1e18 cm⁻

3 and about 3e18 cm<sup>−

3</sup>.

18. The integrated circuit of claim 15, wherein the gate is capable of receiving a voltage, and the voltage is capable of shifting a Fermi-level of the second channel toward a half of a bandgap of the second channel.

19. The integrated circuit of claim 15, wherein a width of the second fin structure is about 30 nm or less.

20. The integrated circuit of claim 15, further comprising:

a shallow trench insulation (STI) layer between the dummy pattern and the FinFET.