Semiconductor device with electrically floating body

• US 8,264,041 B2
• Filed: 01/24/2008
• Issued: 09/11/2012
• Est. Priority Date: 01/26/2007
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Okhonin, Serguei
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US12/019,320
• Publication Number:
  US 20080180995A1
• Time in Patent Office: 1,692 Days
• Field of Search: 257/347, 257/351, 257/E27.112, 257/E21.704, 365/117, 365/181
• US Class Current: 257/347
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion.

Claims

1. A semiconductor device comprising:

a body region configured to be electrically floating;

a gate disposed over a first portion of the body region;

a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion; and

a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion;

wherein the body region extends outside of at least one lateral boundary of the gate at its closest proximity to the gate such that no portion of at least one of the source region and the drain region is disposed directly under the gate.

2. The device of claim 1, comprising a first voltage coupled to the gate, wherein the first voltage may cause minority carriers to accumulate in the first portion of the body region.

3. The device of claim 2, wherein the minority carriers accumulate at a surface region of the first portion of body region that is juxtaposed or near a gate dielectric which is disposed between the gate and the first portion of the body region.

4. The device of claim 2, wherein a region that includes the minority carriers is disconnected from the source region by the second portion of the body region.

5. The device of claim 2, wherein a region that includes the minority carriers is disconnected from the drain region by the third portion of the body region.

6. The device of claim 2, comprising a first potential difference coupled between the source and the drain, the first potential difference generating source current as a result of impact ionization of the minority carriers.

7. The device of claim 6, comprising a second voltage coupled to the gate after and instead of the first voltage, the second voltage causing an accumulation of majority carriers in the first portion of the body region, wherein the majority carriers result in the first data state which is representative of a first charge in the body region.

8. The device of claim 2, comprising a second potential difference coupled between the source and the drain, the second potential difference resulting in a second data state which is representative of a second charge in the body region.

9. The device of claim 1, comprising an insulating layer disposed between the gate and the body region.

10. The device of claim 1, wherein the body region includes a first type of semiconductor material.

11. The device of claim 10, wherein the source region and drain region includes a second type of semiconductor material.

12. The device of claim 11, wherein the source region includes a lightly doped region.

13. The device of claim 11, wherein the source region includes a highly doped region.

14. The device of claim 11, wherein the source region includes a lightly doped region and a highly doped region.

15. The device of claim 11, wherein the drain region includes a lightly doped region.

16. The device of claim 11, wherein the drain region includes a highly doped region.

17. The device of claim 11, wherein the drain region includes a lightly doped region and a highly doped region.

18. A semiconductor device comprising:

a gate;

a body region partially disposed under the gate and electrically floating; and

a source region and a drain region adjacent the body region, wherein one or more of the source region and the drain region include a doped region shaped so that a boundary of the doped region is separated from a portion of the body region underlying the gate;

wherein the body region extends outside of at least one lateral boundary of the gate at its closest proximity to the gate such that no portion of at least one of the source region and the drain region is disposed directly under the gate.

19. A semiconductor device comprising:

a gate;

a body region configured as an electrically floating body, the body region configured so that material forming the body region extends beyond at least one lateral boundary of the gate; and

a source region and a drain region adjacent the body region;

wherein the body region extends outside of at least one lateral boundary of the gate at its closest proximity to the gate such that no portion of at least one of the source region and the drain region is disposed directly under the gate.

20. A transistor comprising:

a floating body region on a insulating substrate;

a gate disposed over a portion of the floating body region; and

a source region and a drain region, wherein a doping profile of one or more of the source and the drain region is configured to prevent formation of a contiguous current channel extending between the source region and the drain region through the floating body region;

wherein the floating body region extends outside of at least one lateral boundary of the gate at its closest proximity to the gate such that no portion of at least one of the source region and the drain region is disposed directly under the gate.