Multi-gate device having a T-shaped gate structure

• US 8,264,048 B2
• Filed: 02/15/2008
• Issued: 09/11/2012
• Est. Priority Date: 02/15/2008
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Rachmady, Willy, Shah, Uday, Kavalieros, Jack T.
• Primary Examiner(s): Tran, Long K.
• Assistant Examiner(s): KLEIN, JORDAN M
• Application Number:
  US12/032,603
• Publication Number:
  US 20090206406A1
• Time in Patent Office: 1,670 Days
• Field of Search: 257/213, 257/288, 257/386, 257/401, 257/E29.264, 257/E21.421, 257/331, 257/365, 257/623
• US Class Current: 257/401
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source region, and a drain region, the gate region being positioned between the source and drain regions, a gate dielectric coupled to the gate region of the multi-gate fin, a gate electrode coupled to the gate dielectric, the gate electrode having a first thickness and a second thickness, the second thickness being greater than the first thickness, a first spacer dielectric coupled to a portion of the gate electrode having the first thickness, and a second spacer dielectric coupled to the first spacer dielectric and coupled to the gate electrode where the second spacer dielectric is coupled to a portion of the gate electrode having the second thickness.

Claims

1. An apparatus, comprising:

a semiconductor substrate;

at least one multi-gate fin coupled with the semiconductor substrate, the at least one multi-gate fin comprising a first side, a second side, a third side and a fourth side, the fourth side of the at least one multi-gate fin being adjacent to the semiconductor substrate, the multi-gate fin further comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions;

a gate electrode coupled to a gate dielectric, the gate electrode comprising a first portion comprising a first thickness and a second portion comprising a second thickness, the second thickness being greater than the first thickness, the first and second thicknesses extending between the source and drain regions, the first portion of the gate electrode comprising surfaces that correspond to a first part of the first, second and third sides of the at least one multi-gate fin and the second portion of the gate electrode comprising surfaces that correspond to a second and a third part of the first, second and third sides of the at least one multi-gate fin, the first part of the first, second and third sides of the at least one multi-gate fin being disposed between the second and third parts of the first, second and third sides of the at least one multi-gate fin, and a cross-section of the gate electrode along the multi-gate fin having a substantially T-shaped structure; and

the gate dielectric being coupled to the first, second and third parts of the first, second and third sides of the gate region of the multi-gate fin and the gate electrode between the gate region of the multi-gate fin and the gate electrode, the gate dielectric being coupled to the surfaces of the first portion of the gate electrode corresponding to the first, second and third sides of the gate region of the at least one multi-gate fin, and to the surfaces of the second portion of the gate electrode corresponding to the first, second and third sides of the gate region of the at least one multi-gate fin.

2. An apparatus according to claim 1, further comprising:

a first spacer dielectric coupled to the portion of the gate electrode comprising the first thickness; and

a second spacer dielectric coupled to the portion of the gate electrode comprising the second thickness,

wherein the first spacer dielectric comprises silicon nitride and the second spacer dielectric comprises carbon-doped silicon nitride.

3. An apparatus according to claim 1 wherein the semiconductor substrate comprises silicon, the multi-gate fin comprises silicon, the gate dielectric comprises a high-k gate oxide, and the gate electrode comprises a workfunction metal.

4. An apparatus according to claim 1 wherein the multi-gate fin is a tri-gate fin that is part of a transistor having a gate length of about 22 nm or less.

5. An apparatus according to claim 1, further comprising:

a first spacer dielectric coupled to a first portion of the gate dielectric that is coupled to the first portion of the gate electrode comprising the first thickness; and

a second spacer dielectric coupled to the first spacer dielectric and coupled to a second portion of the gate dielectric that is coupled to the second portion of the gate electrode comprising the second thickness.

6. An apparatus according to claim 5, wherein the semiconductor substrate comprises silicon, the multi-gate fin comprises silicon, the gate dielectric comprises a high-k gate oxide, and the gate electrode comprises a workfunction metal.

7. An apparatus according to claim 6, wherein the first spacer dielectric comprises silicon nitride and the second spacer dielectric comprises carbon-doped silicon nitride.

8. An apparatus according to claim 7, wherein the multi-gate fin is a tri-gate fin that is part of a transistor having a gate length of about 22 nm or less.

9. An apparatus, comprising:

a silicon substrate;

at least one silicon multi-gate fin coupled with the silicon substrate, the at least one multi-gate fin comprising a first side, a second side, a third side and a fourth side, the fourth side of the at least one multi-gate fin being adjacent to the semiconductor substrate, the multi-gate fin further comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions;

a gate electrode coupled to a gate dielectric, the gate electrode comprising a first portion comprising a first thickness and a second portion comprising a second thickness, the second thickness being greater than the first thickness, the first and second thicknesses extending between the source and drain regions, the first portion of the gate electrode comprising surfaces that correspond to a first part of the first, second and third sides of the at least one multi-gate fin and the second portion of the gate electrode comprising surfaces that correspond to a second and a third part of the first, second and third sides of the at least one multi-gate fin, the first part of the first, second and third sides of the at least one multi-gate fin being disposed between the second and third parts of the first, second and third sides of the at least one multi-gate fin, the gate electrode comprising a workfunction metal and the gate dielectric comprising a high-k gate oxide, and a cross-section of the gate electrode along the multi-gate fin having a substantially T-shaped structure; and

the gate dielectric being coupled to the first, second and third parts of the first, second and third sides of the gate region of the multi-gate fin and the gate electrode between the gate region of the multi-gate fin and the gate electrode, the gate dielectric being coupled to the surfaces of the first portion of the gate electrode corresponding to the first, second and third sides of the gate region of the at least one multi-gate fin, and to the surfaces of the second portion of the gate electrode corresponding to the first, second and third sides of the gate region of the at least one multi-gate fin.

10. An apparatus according to claim 9, further comprising:

a first spacer dielectric coupled to a first portion of the gate dielectric that is coupled to the first portion of the gate electrode comprising the first thickness; and

a second spacer dielectric coupled to the first spacer dielectric and coupled to a second portion of the gate dielectric that is coupled to the second portion of the gate electrode comprising the second thickness.

11. An apparatus according to claim 10, wherein the first spacer dielectric comprises silicon nitride and the second spacer dielectric comprises carbon-doped silicon nitride.

12. An apparatus according to claim 11, wherein the multi-gate fin is a tri-gate fin that is part of a transistor having a gate length of about 22 nm or less.