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Through silicon via (TSV) wire bond architecture

  • US 8,264,067 B2
  • Filed: 07/16/2010
  • Issued: 09/11/2012
  • Est. Priority Date: 10/09/2009
  • Status: Active Grant
First Claim
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1. An integrated circuit (IC) comprising:

  • a substrate with a top surface and a bottom surface, wherein circuitry is formed on the top surface;

    a plurality of bonding pads formed along a periphery of the bottom surface, wherein a first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV); and

    a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads, the BML configured to distribute electrical signals provided by the second subset of bonding pads, wherein the BML is formed within a boundary created by the plurality of bonding pads.

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