Through silicon via (TSV) wire bond architecture
First Claim
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1. An integrated circuit (IC) comprising:
- a substrate with a top surface and a bottom surface, wherein circuitry is formed on the top surface;
a plurality of bonding pads formed along a periphery of the bottom surface, wherein a first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV); and
a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads, the BML configured to distribute electrical signals provided by the second subset of bonding pads, wherein the BML is formed within a boundary created by the plurality of bonding pads.
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Abstract
A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads.
55 Citations
19 Claims
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1. An integrated circuit (IC) comprising:
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a substrate with a top surface and a bottom surface, wherein circuitry is formed on the top surface; a plurality of bonding pads formed along a periphery of the bottom surface, wherein a first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV); and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads, the BML configured to distribute electrical signals provided by the second subset of bonding pads, wherein the BML is formed within a boundary created by the plurality of bonding pads. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit (IC) comprising:
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a substrate with a top surface and a bottom surface, wherein circuitry is disposed on the top surface; a first bonding pad disposed on the bottom surface, the first bonding pad electrically coupled to circuitry on the top surface with a through silicon via (TSV); a backside metal layer (BML) disposed on the bottom surface and electrically coupled to a second bonding pad disposed on the bottom surface, the BML configured to distribute a first signal provided by the second bonding pad; and a power ring disposed about a periphery of the substrate, the power ring to distribute power to circuitry formed on the top surface. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A three-dimensional stacked multi-chip module comprising:
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a first integrated circuit (IC) comprising a first substrate with a first top surface and a first bottom surface, wherein circuitry is formed on the first top surface; a second IC, the second IC comprising, a second substrate with a second top surface and a second bottom surface, wherein circuitry is formed on the second top surface, a first plurality of bonding pads formed in a ring structure along a periphery of the second bottom surface, wherein a first subset of bonding pads in the first plurality of bonding pads is electrically coupled to circuitry on the second top surface with through silicon vias (TSV), and a backside metal layer (BML) formed within the ring structure on the second bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads, the BML configured to distribute electrical signals provided by the second subset of bonding pads; and wherein the first IC is attached to the second IC. - View Dependent Claims (16, 17, 18, 19)
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Specification