Semiconductor memory device having an electrically floating body transistor

• US 8,264,876 B2
• Filed: 09/26/2011
• Issued: 09/11/2012
• Est. Priority Date: 10/04/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US13/245,224
• Publication Number:
  US 20120081941A1
• Time in Patent Office: 351 Days
• Field of Search: 365/177, 365/189.09
• US Class Current: 365/177
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/73 Bipolar junction transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor memory cell is formed in a semiconductor. The semiconductor memory cell includes: a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and a buried region located within the semiconductor memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type.

Claims

1. A semiconductor memory cell formed in a semiconductor, the semiconductor memory cell comprising:

a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and

a buried region located within the semiconductor memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type,

wherein the floating body region is bounded on the sides by at least a first insulating region having a first thickness and a second insulating region having a second thickness, wherein the second thickness is different from the first thickness.

2. The semiconductor memory cell of claim 1, further comprising a bit line region at said surface, the bit line region having the second conductivity type.

3. The semiconductor memory cell of claim 1, further comprising a gate above said surface and insulated from said surface by an insulating layer.

4. The semiconductor memory cell of claim 1, further comprising a first well region of the first conductivity type beneath the buried region.

5. The semiconductor memory cell of claim 1, wherein said buried region is adapted to receive electrical signals of different amplitude or polarity, and wherein said electrical signals depend on an operation of said semiconductor memory cell.

6. The semiconductor memory cell of claim 2, further comprising a single shared contact through which bit line regions of adjacent memory cells are coupled.

7. The semiconductor memory cell of claim 2, further comprising a common region through which bit line regions of adjacent cells are coupled, the common region having the second conductivity type.

8. An array of memory cells formed in a semiconductor, the array comprising:

a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of said memory cells comprising;

a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and

a buried region located beneath the surface of the memory cell, wherein the buried region has a second conductivity type,

wherein the floating body region is bounded on the sides by at least a first insulating region having a first thickness and a second insulating region having a second thickness, wherein the second thickness is different from the first thickness.

9. The array of semiconductor memory cells of claim 8, wherein each of said semiconductor memory cells further comprises a bit line region located in the floating body region and substantially exposed at said surface, the bit line region having the second conductivity type.

10. The array of memory cells of claim 8, further comprising a plurality of source lines crossing the array in a first direction beneath said surface, wherein the plurality of source lines are coupled to said buried regions.

11. The array of memory cells of claim 10, further comprising a plurality of bit lines crossing the array in a second direction substantially orthogonal to the first direction, wherein the plurality of bit lines are coupled at said surface to said bit line regions.

12. The array of memory cells of claim 8, wherein each of said memory cells further comprises a gate region above said surface and insulated from said surface by an insulating layer.

13. The array of memory cells of claim 8, wherein each of said semiconductor memory cells further comprises a first well region of the first conductivity type beneath the buried region.

14. The array of memory cells of claim 8, wherein each of said buried regions is adapted to receive electrical signals of different amplitude or polarity, wherein the electrical signals depend on an operation of each of said memory cells.

15. The array of memory cells of claim 8, further comprising a voltage generator circuitry configured to apply a voltage to said buried regions.

16. The array of memory cells of claim 8,

wherein a first memory cell of the plurality of memory cells is disposed in a first row of the plurality of rows and in a first column of the plurality of columns;

wherein a second memory cell of the plurality of memory cells is disposed in a second row of the plurality of rows and in the first column of the plurality of columns, the second row being adjacent to the first row;

wherein a third memory cell of the plurality of memory cells is disposed in a third row of the plurality of rows and in the first column of the plurality of columns, the third row being adjacent to the second row; and

wherein a fourth memory cell of the plurality of memory cells is disposed in a fourth row of the plurality of rows and in the first column of the plurality of columns, the fourth row being adjacent to the third row;

the array further comprising;

a first word line of a plurality of word lines coupled to a gate region of the first memory cell and a gate region of the second memory cell; and

a second word line of a plurality of word lines coupled to a gate region of the third memory cell and a gate region of the fourth memory cell.

17. The array of memory cells of claim 10,

wherein a first memory cell of the plurality of memory cells is disposed in a first row of the plurality of rows and in a first column of the plurality of columns;

wherein a second memory cell of the plurality of memory cells is disposed in a second row of the plurality of rows and in the first column of the plurality of columns, the second row being adjacent to the first row;

wherein a third memory cell of the plurality of memory cells is disposed in a third row of the plurality of rows and in the first column of the plurality of columns, the third row being adjacent to the second row;

wherein a fourth memory cell of the plurality of memory cells is disposed in a fourth row of the plurality of rows and in the first column of the plurality of columns, the fourth row being adjacent to the third row;

wherein a first source line of the plurality of source lines is coupled to a source line region of the first memory cell;

wherein a second source line of the plurality of source lines is coupled to a source line region of the second memory cell and a source line region of the third memory cell; and

wherein a third source line of the plurality of source lines is coupled to a source line region of the fourth memory cell.

18. The array of memory cells of claim 9,

wherein a first memory cell of the plurality of memory cells is disposed in a first row of the plurality of rows and in a first column of the plurality of columns;

wherein a second memory cell of the plurality of memory cells is disposed in a second row of the plurality of rows and in the first column of the plurality of columns, the second row being adjacent to the first row;

wherein a third memory cell of the plurality of memory cells is disposed in a third row of the plurality of rows and in the first column of the plurality of columns, the third row being adjacent to the second row;

wherein the bit line region of the second memory cell and the bit line region of the third memory cell are coupled to a terminal through a single shared contact.

19. The array of memory cells of claim 9,

wherein a first memory cell of the plurality of memory cells is disposed in a first row of the plurality of rows and in a first column of the plurality of columns;

wherein a second memory cell of the plurality of memory cells is disposed in a second row of the plurality of rows and in the first column of the plurality of columns, the second row being adjacent to the first row;

wherein a third memory cell of the plurality of memory cells is disposed in a third row of the plurality of rows and in the first column of the plurality of columns, the third row being adjacent to the second row;

wherein a common region of the second conductivity type is disposed at the semiconductor surface; and

wherein said common region couples the bit line region of the second memory cell to the bit line region of the third memory cell.

20. An integrated circuit comprising:

an array of memory cells formed in a semiconductor having at least one surface, the array comprising;

a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell comprising;

a floating body region having a first conductivity type, wherein a surface of the semiconductor defines at least a portion of the floating body region;

a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type; and

a bit line region having the second conductivity type located within the floating body region and substantially exposed at the surface,

wherein the floating body region is bounded on the sides by at least a first insulating region having a first thickness and a second insulating region having a second thickness, wherein the second thickness is different from the first thickness; and

a first control circuit to provide electrical signals to said bit line regions, wherein said electrical signals have an amplitude or polarity dependent on an operation of said array of memory cells.

21. The integrated circuit of claim 20, wherein said electrical signals provided to said bit line region comprise one of at least three amplitude or polarity values.

22. The integrated circuit of claim 20, further comprising a second control circuit to provide electrical signals to said buried region, wherein said electrical signals to said buried region have an amplitude or polarity dependent on an operation of said array of memory cells.

23. The integrated circuit of claim 20, wherein said array of memory cells further comprises a plurality of bit lines crossing the array in a first direction, the plurality of bit lines coupled at the surface to the bit line region of each memory cell.

24. The integrated circuit of claim 20, wherein said array of memory cells further comprises a plurality of source lines crossing the array in a second direction substantially orthogonal to the first direction beneath the surface, the plurality of source lines being coupled to said buried region of each memory cell.

25. The integrated circuit of claim 20, wherein each of said array of memory cells further comprises a gate region above said surface and insulated from said surface by an insulating layer.

26. The integrated circuit of claim 20, wherein each of said memory cells further comprises a well region of the first conductivity type beneath the buried region.

27. The integrated circuit of claim 20, wherein said array of memory cells comprises:

a first memory cell of the plurality of memory cells disposed in a first row of the plurality of rows and in a first column of the plurality of columns;

a second memory cell of the plurality of memory cells disposed in a second row of the plurality of rows and in the first column of the plurality of columns, wherein the second row is adjacent to the first row;

a third memory cell of the plurality of memory cells disposed in a third row of the plurality of rows and in the first column of the plurality of columns, wherein the third row is adjacent to the second row;

a fourth memory cell of the plurality of memory cells disposed in a fourth row of the plurality of rows and in the first column of the plurality of columns, wherein the fourth row is adjacent to the third row;

a first word line of a plurality of word lines coupled to a gate region of the first memory cell and a gate region of the second memory cell; and

a second word line of a plurality of word lines coupled to a gate region of the third memory cell and a gate region of the fourth memory cell.

28. The integrated circuit of claim 24, wherein said array of memory cells comprises:

a first memory cell of the plurality of memory cells disposed in a first row of the plurality of rows and in a first column of the plurality of columns;

a second memory cell of the plurality of memory cells disposed in a second row of the plurality of rows and in the first column of the plurality of columns, wherein the second row is adjacent to the first row;

a third memory cell of the plurality of memory cells disposed in a third row of the plurality of rows and in the first column of the plurality of columns, wherein the third row is adjacent to the second row;

a fourth memory cell of the plurality of memory cells disposed in a fourth row of the plurality of rows and in the first column of the plurality of columns, wherein the fourth row is adjacent to the third row;

a first source line of the plurality of source lines coupled to a source line region of the first memory cell;

a second source line of the plurality of source lines coupled to a source line region of the second memory cell and a source line region of the third memory cell; and

a third source line of the plurality of source lines coupled to a source line region of the fourth memory cell.

29. The integrated circuit of claim 20, wherein said array of memory cells comprises:

a first memory cell of the plurality of memory cells disposed in a first row of the plurality of rows and in a first column of the plurality of columns;

a second memory cell of the plurality of memory cells disposed in a second row of the plurality of rows and in the first column of the plurality of columns, wherein the second row is adjacent to the first row;

a third memory cell of the plurality of memory cells disposed in a third row of the plurality of rows and in the first column of the plurality of columns;

wherein the third row is adjacent to the second row; and

wherein the bit line region of the second memory cell and the bit line region of the third memory cell are coupled to a terminal through a single shared contact.

30. The integrated circuit of claim 20, wherein said array of memory comprises:

a first memory cell of the plurality of memory cells disposed in a first row of the plurality of rows and in a first column of the plurality of columns;

a second memory cell of the plurality of memory cells disposed in a second row of the plurality of rows and in the first column of the plurality of columns, wherein the second row is adjacent to the first row;

a third memory cell of the plurality of memory cells disposed in a third row of the plurality of rows and in the first column of the plurality of columns, wherein the third row is adjacent to the second row;

a common region of the second conductivity type;

wherein said common region is disposed at the semiconductor surface; and

wherein said common region couples the bit line region of the second memory cell to the bit line region of the third memory cell.