Method for memory cell erasure with a programming monitor of reference cells

• US 8,264,885 B2
• Filed: 04/08/2011
• Issued: 09/11/2012
• Est. Priority Date: 05/27/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira, Mihnea, Andrei
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US13/082,965
• Publication Number:
  US 20110188312A1
• Time in Patent Office: 522 Days
• Field of Search: 365/185.29, 365/185.33, 365/185.11, 365/185.19, 365/185.2, 365/185.22, 365/185.17
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells

Abstract

Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.

Claims

1. A memory device comprising:

an array of memory cells including a number of data cells and a number of reference cells; and

control circuitry coupled to the array of memory cells and configured to;

as a part of an erase operation performed on a selected group of memory cells, perform a programming monitor operation on the number of reference cells prior to performing a programming operation on at least some of the number of data cells; and

at least partially based on the programming monitor operation, adjusting voltages associated with operating the at least some of the number of data cells.

2. The memory device of claim 1, wherein the number of reference cells each have a control gate coupled to one of a number of access lines of the array, and wherein the control circuitry is configured to:

perform the programming monitor operation by applying a particular voltage pulse to the control gates of the respective ones of the number of reference cells; and

determine a program performance of the respective ones of the number of reference cells.

3. The memory device of claim 2, wherein the control circuitry is configured to determine the program performance of the respective ones of the number of reference cells by:

applying a particular read voltage to the control gates of the respective ones of the number of reference cells; and

determining an amount of the respective ones of the number of reference cells that conduct current in response to the application of the particular read voltage.

4. The memory device of claim 3, wherein the control circuitry is configured to adjust voltages by selecting a particular set of adjusted operating voltages from a number of sets of operating voltages based on the determined amount of the number of reference cells that conduct current.

5. The memory device of claim 4, wherein trim data corresponding to the selected particular set of adjusted operating voltages is stored by at least some of the number of reference cells.

6. The memory device of claim 4, wherein the selected particular set of adjusted operating voltages includes a programming start voltage, a program step voltage, and an erase verify voltage.

7. A memory device, comprising:

an array of memory cells including data cells and reference cells; and

control circuitry coupled to the array of memory cells and configured to;

as a part of an erase operation, apply a programming voltage pulse having a particular magnitude to a control gate of each of a number of reference cells;

determine an amount of the number of reference cells whose threshold voltage reaches a particular level in response to the applied programming voltage pulse;

select an adjusted set of particular operating voltages based, at least partially, on the determined amount of the number of reference cells whose threshold voltage reaches the particular level in response to the applied programming voltage pulse; and

program a number of data cells using at least one adjusted programming voltage from the adjusted set of particular operating voltages.

8. The memory device of claim 7, wherein the at least one adjusted programming voltage includes an adjusted programming start voltage, and wherein the control circuitry is configured to:

adjust at least one of;

the particular magnitude of the programming voltage pulse applied to the control gate of each of the number of reference cells; and

the particular level, based on the determined amount of the number of reference cells whose threshold voltage reaches the particular level in response to the applied programming voltage pulse.

9. The memory device of claim 7, wherein the array includes at least one block of memory cells and wherein the at least one block includes a number of NAND strings of reference cells which are distributed throughout the at least one block.

10. The memory device of claim 7, wherein the array includes at least one block of memory cells and wherein the at least one block includes only one NAND string of reference cells.

11. The memory device of claim 7, wherein the array includes at least one block of memory cells and wherein only one word line of the at least one block is coupled to reference cells.

12. A memory device, comprising:

an array of memory cells including data cells and reference cells; and

control circuitry coupled to the array and configured to;

perform an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells, wherein the number of data cells are associated with a number of particular operating parameters;

as a part of the erase operation and prior to programming the number of data cells, apply a voltage pulse having a particular magnitude to the number of reference cells;

determine an amount of the number of reference cells whose threshold voltage reaches a particular level in response to the applied voltage pulse; and

adjust at least one of the number of particular operating parameters associated with the number of data cells based on the determined amount of the number of reference cells.

13. The memory device of claim 12, wherein the control circuitry is configured to adjust a magnitude of an initial programming pulse of a series of incremented programming pulses used to program the number of data cells.

14. The memory device of claim 13, wherein the control circuitry is configured to decrease the magnitude of the initial programming pulse of the series of incremented programming pulses used to program the number of data cells.

15. The memory device of claim 13, wherein the control circuitry is configured to adjust a step size associated with the series of incremented programming pulses used to program the number of data cells.

16. The memory device of claim 15, wherein the control circuitry is configured to decrease the magnitude of the step size associated with the series of incremented programming pulses used to program the number of data cells.

17. The memory device of claim 12, wherein:

the selected group of memory cells is a selected block of memory cells of a number of blocks of memory cells in the array;

each of the number of blocks includes a number of reference cells, a number of data cells, and a number of particular operating voltages associated with operating the number of data cells;

the number of data cells of at least one of the number of blocks is associated with at least one operating voltage different from the number of particular operating voltages associated with the number of data cells of the selected block; and

wherein the control circuitry is configured to method adjust at least one of the number of particular operating voltages associated with the number of data cells in each of the number of blocks on block by block basis.

18. A memory device, comprising:

an array of memory cells including data cells and reference cells; and

control circuitry coupled to the array and configured to;

select a first block of a number of blocks of memory cells having a number of data cells and a number of reference cells, each of the number of blocks having an associated set of particular operating parameters used to program the number of data cells;

perform an erase operation on the number of data cells and the number of reference cells of the selected first block;

as a part of the erase operation, perform a programming monitor operation on the number of reference cells of the selected first block before programming the number of data cells of the selected first block; and

adjust at least one of the associated set of particular operating parameters used to program the number of data cells of the selected first block based, at least partially, on the programming monitor operation performed on the number of reference cells of the selected first block.

19. The memory device of claim 18, wherein performing the programming monitor operation includes:

applying a voltage pulse having a particular magnitude to a control gate of each of the number of reference cells; and

determining an amount of the number of reference cells whose threshold voltage reaches a particular level in response to the applied voltage pulse.

20. The memory device of claim 19, wherein the control circuitry is configured to sense a current conducted by a number of bit lines to which the number of reference cells are coupled to determine the amount of the number of reference cells whose threshold voltage reaches the particular level.

21. The memory device of claim 18, wherein the control circuitry is configured to:

select at least a second block;

perform an erase operation on the number of data cells and the number of reference cells of the at least a second block;

perform the programming monitor operation on the number of reference cells of the selected at least second block before programming the number of data cells of the selected at least second block; and

adjust at least one of the associated set of particular operating parameters used to program the number of data cells of the selected at least second block based on the programming monitor operation performed on the number of reference cells of the selected at least second block.

22. The memory device of claim 21, wherein the control circuitry is configured to adjust the at least one of the associated set of particular operating parameters used to program the number of data cells of the selected at least second block by a different amount than the at least one of the associated set of particular operating parameters used to program the number of data cells of the selected first block.