Systems and methods for refreshing a memory module

• US 8,264,903 B1
• Filed: 05/05/2010
• Issued: 09/11/2012
• Est. Priority Date: 05/05/2009
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Lee, Hyun, Bhakta, Jayesh R.
• Primary Examiner(s): Lam, David
• Application Number:
  US12/774,632
• Time in Patent Office: 860 Days
• Field of Search: 365/222, 365/194, 365/233.13, 365/230.03, 365/233.1
• US Class Current: 365/222
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory module according to certain aspects has a plurality of memory devices arranged into one or more logical ranks. Each logical rank may correspond to a set of at least two physical ranks. The memory module can include a circuit operatively coupled to the plurality of memory devices and configured to be operatively coupled to a memory controller of a computer system to receive a logical rank refresh command. In response, the circuit can initiate a first refresh operation for one or more first physical ranks and then initiate a second refresh operation for one or more second physical ranks. The memory module can further include a memory location storing a refresh time (tRFC) value accessible by the memory controller and based at least in part on a calculated maximum amount of time for refreshing the logical rank.

Claims

1. A memory module comprising:

a plurality of memory devices arranged into one or more logical ranks, each logical rank corresponding to a set of at least two physical ranks;

a circuit operatively coupled to the plurality of memory devices and configured to be operatively coupled to a memory controller of a computer system to receive, for a logical rank of the one or more logical ranks, a logical rank refresh command generated by the memory controller, the circuit configured to initiate, in response to the logical rank refresh command, a first refresh operation for one or more first physical ranks of the set of at least two physical ranks and a second refresh operation for one or more second physical ranks of the set of at least two physical ranks, wherein the second refresh operation is initiated after the first refresh operation; and

a memory location storing a refresh time (tRFC) value based at least in part on a calculated maximum amount of time for refreshing the logical rank, wherein the tRFC value is accessible by the memory controller.

2. The memory module of claim 1, wherein the memory location resides in a serial presence detect (SPD) device operatively coupled to the circuit and accessible by the memory controller, and wherein the circuit is configured to cause the tRFC value to be stored in the SPD device.

3. The memory module of claim 1, wherein the circuit is configured to calculate the tRFC value.

4. The memory module of claim 3, wherein the circuit is configured to calculate the tRFC value in response to at least a maximum amount of time it takes to refresh a physical rank, the number of physical ranks per logical rank, and a maximum number of continuous clock cycles that commands generated by the memory controller can occupy the command bus.

5. The memory module of claim 4, wherein the circuit is configured to calculate the tRFC value according to the equation:

tRFC=(PR_refresh_time*num_—

PR_per_—

LR)+(bus_wait*clk_per)

where PR_refresh_time is an amount of time it takes to refresh a physical rank, num_PR_per_LR is the number of physical ranks corresponding to a logical rank, bus_wait is a maximum number of continuous clock cycles that commands generated by the memory controller can occupy the command bus, and clk_per is a system clock period.

6. The memory module of claim 5, wherein ratio of the number of physical ranks to the number of logical ranks is two.

7. The memory module of claim 3, wherein the circuit is configured to calculate the tRFC value at least in part based on a four activate window (tFAW) value.

8. The memory module of claim 7, wherein the circuit is configured to calculate the tRFC value according to the equation:

tRFC≧

(PR_refresh_time*num_—

PR_per_—

LR)+(tFAW−

num_open_slots)*clk_per

where PR_refresh_time is an amount of time it takes to refresh a physical rank, num_PR_per_LR is the number of physical ranks corresponding to a logical rank, tFAW is the four activate window value, and num_open_slots is a minimum number of open slots within the tFAW in which there is not a memory controller command on the command bus, and clk_per is a system clock period.

9. The memory module of claim 1, wherein the one or more first physical ranks comprise at least two physical ranks and the one or more second physical ranks comprise of at least two physical ranks.

10. The memory module of claim 9, wherein ratio of the number of physical ranks to the number of logical ranks is 4, 8, or 16.

11. The memory module of claim 1, wherein the one or more first physical ranks comprise N physical ranks configured to be refreshed concurrently with one another and wherein the one or more second physical ranks comprise N physical ranks configured to be refreshed concurrently with one another, where N is a number greater than or equal to two.

12. The memory module of claim 11, wherein the circuit is configured to calculate the tRFC value according to the equation:

13. The memory module of claim 1, wherein the memory devices are DDR memory devices and the memory module further comprises a printed circuit board configured to be operatively coupled to the memory controller, the circuit and the plurality of memory devices mounted on the printed circuit board.

14. The memory module of claim 1, wherein each logical rank comprises an address space which is mapped into an address space of a set of at least two of the plurality of physical ranks.

15. A method of using a memory module, comprising:

providing a memory module comprising a plurality of memory devices arranged into one or more logical ranks, each logical rank corresponding to a set of at least two physical ranks;

receiving a command to refresh a logical rank of the one or more logical ranks;

initiating a refresh operation for one or more first physical ranks of the set of physical ranks corresponding to the logical rank in response to the command; and

initiating a refresh operation for one or more second physical ranks of the set of physical ranks corresponding to the logical rank in response to the command; and

storing a refresh time (tRFC) value in a memory location of the memory module, the tRFC value based at least in part on a calculated maximum amount of time for refreshing the logical rank, wherein the tRFC value is accessible by the memory controller.

16. The method of claim 15, wherein the tRFC value is calculated in response to at least a maximum amount of time it takes to refresh a physical rank, the number of physical ranks per logical rank, and a maximum number of continuous clock cycles that commands generated by the memory controller can occupy the command bus.

17. The method of claim 16, wherein the tRFC value is calculated according to the equation:

tRFC=(PR_refresh_time*num_—

PR_per_—

LR)+(bus_wait*clock_per)

where PR_refresh_time is an amount of time it takes to refresh a physical rank, num_PR_per_LR is the number of physical ranks corresponding to a logical rank, bus_wait is a maximum number of continuous clock cycles that commands generated by the memory controller can occupy the command bus, and clock_per is a system clock period.

18. The method of claim 17, wherein the tRFC value is calculated at least in part based on a four activate window (tFAW) value.

19. The method of claim 18, wherein the tRFC value is calculated according to the equation:

tRFC≧

(PR_refresh_time*num_—

PR_per_—

LR)+(tFAW−

num_open_slots)*clk_per

where PR_refresh_time is an amount of time it takes to refresh a physical rank, num_PR_per_LR is the number of physical ranks corresponding to a logical rank, tFAW is the four activate window value, and num_open_slots is a minimum number of open slots within the tFAW in which there is not a memory controller command on the command bus, and clk_per is a system clock period.

20. The method of claim 15, wherein the one or more first physical ranks comprise N physical ranks configured to be refreshed concurrently with one another and wherein the one or more second physical ranks comprise N physical ranks configured to be refreshed concurrently with one another, where N is a number greater than or equal to two.

21. The method of claim 20, wherein the tRFC value is calculated according to the equation:

22. The method of claim 16, further comprising calculating the tRFC value prior to storing the tRFC value in the memory location of the memory module.

23. The method of claim 22, wherein the calculating step is performed by a circuit mounted on the memory module.

24. A method of using a memory module, comprising:

accessing a refresh time (tRFC) value from a memory module comprising a plurality of memory devices arranged into one or more logical ranks, each logical rank corresponding to a set of at least two physical ranks, the tRFC value based at least in part on a calculated maximum amount of time for refreshing the logical rank;

transmitting a refresh command to the memory module instructing the memory module to refresh a logical rank of the one or more logical ranks, the refresh command causing the memory module to initiate a refresh operation for one or more first physical ranks of the set of at least two physical ranks and to initiate a second refresh operation for one or more second physical ranks of the set of at least two physical ranks, wherein the second refresh operation is initiated after the first refresh operation; and

after transmitting the refresh command to the memory module, waiting for an amount of time corresponding to at least the tRFC value before issuing a subsequent refresh command to the memory module.

25. The method of claim 24, wherein the receiving, transmitting and waiting are performed by a memory controller of a computer system.