Specialized processing block for programmable logic device

• US 8,266,198 B2
• Filed: 06/05/2006
• Issued: 09/11/2012
• Est. Priority Date: 02/09/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lee, Kwan Yee Martin, Langhammer, Martin, Lin, Yi-Wen, Nguyen, Triet M.
• Primary Examiner(s): Ngo, Chuong D
• Assistant Examiner(s): SANDIFER, MATTHEW D
• Application Number:
  US11/447,329
• Publication Number:
  US 20070185951A1
• Time in Patent Office: 2,290 Days
• Field of Search: 708497-498, 708551-553, 326 37- 39
• US Class Current: 708/523
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/49947 Rounding
• CPC Class Codes: G06F 7/49963 Rounding to nearest G06F7/49957 takes precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.

Claims

1. A specialized processing block for a programmable logic device, said specialized processing block comprising:

arithmetic circuitry for providing products of inputs and sums of said products to output a result, said arithmetic circuitry comprising a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators having a respective pair of inputs different from inputs of each other one of said partial product generators and providing a respective plurality of vectors representing a respective partial product,

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product, and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products;

said specialized processing block further comprising;

rounding circuitry that provides both;

a first user-selectable option to round said result to a nearest integer, and

a second user-selectable option to round said result to a nearest even integer.

2. The specialized processing block of claim 1 wherein said rounding circuitry accepts input of a variable that encodes a bit position at which rounding of said result is performed.

3. The specialized processing block of claim 1 wherein:

said arithmetic circuitry operates on values in a range that extends up to a most highly positive value and down to a most highly negative value;

said specialized processing block further comprising;

saturation circuitry for clipping said result to a value inside said range;

wherein;

said saturation circuitry accepts input of a variable that encodes a bit position at which saturation of said result is performed.

4. The specialized processing block of claim 3 wherein said saturation circuitry clips said results symmetrically.

5. The specialized processing block of claim 3 wherein said saturation circuitry clips said results asymmetrically.

6. The specialized processing block of claim 3 wherein said saturation circuitry operates after said rounding circuitry.

7. The specialized processing block of claim 1 wherein said rounding circuitry is programmably locatable to optimize operation of said specialized processing block.

8. The specialized processing block of claim 7 wherein at least a first portion of said rounding circuitry is programmably locatable in parallel with at least a portion of said arithmetic circuitry to operate in a look-ahead mode.

9. The specialized processing block of claim 8 wherein:

said portion of said arithmetic circuitry computes said result without rounding;

said first portion of said rounding circuitry computes said result with rounding in parallel with computation by said portion of said arithmetic circuitry of said result without rounding; and

said rounding circuitry further comprises a second portion that selects between said result with rounding and said result without rounding.

10. The specialized processing block of claim 7 wherein:

said arithmetic circuitry includes a register creating a critical timing path; and

said rounding circuitry is programmably locatable in at least one position that is at least one of (a) before, and (b) after, said register so as to be programmably includable in, and excludable from, said critical timing path.

11. The specialized processing block of claim 10 wherein said critical timing path includes results chained from another said specialized processing block.

12. A programmable logic device comprising the specialized processing block of claim 1.

13. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 12 coupled to the processing circuitry and the memory.

14. A printed circuit board on which is mounted a programmable logic device as defined in claim 12.

15. The printed circuit board defined in claim 14 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

16. The printed circuit board defined in claim 15 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

17. An integrated circuit device comprising the specialized processing block of claim 1.

18. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

an integrated circuit device as defined in claim 17 coupled to the processing circuitry and the memory.

19. A printed circuit board on which is mounted an integrated circuit device as defined in claim 18.

20. The printed circuit board defined in claim 19 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

21. The printed circuit board defined in claim 20 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

22. A specialized processing block for a programmable logic device, said specialized processing block comprising:

arithmetic circuitry that operates on values in a range that extends up to a most highly positive value and down to a most highly negative value for providing products of inputs and sums of said products to output a result, said arithmetic circuitry comprising a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators having a respective pair of inputs different from inputs of each other one of said partial product generators and providing a respective plurality of vectors representing a respective partial product,

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product, and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products;

said specialized processing block further comprising;

saturation circuitry for clipping said result to a value inside said range;

wherein;

said saturation circuitry accepts input of a variable that encodes a bit position at which saturation of said result is performed.

23. The specialized processing block of claim 22 wherein said saturation circuitry clips said results symmetrically.

24. The specialized processing block of claim 22 wherein said saturation circuitry clips said results asymmetrically.

25. A programmable logic device comprising the specialized processing block of claim 22.

26. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 25 coupled to the processing circuitry and the memory.

27. A printed circuit board on which is mounted a programmable logic device as defined in claim 25.

28. The printed circuit board defined in claim 27 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

29. The printed circuit board defined in claim 28 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

30. An integrated circuit device comprising the specialized processing block of claim 22.

31. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

an integrated circuit device as defined in claim 30 coupled to the processing circuitry and the memory.

32. A printed circuit board on which is mounted an integrated circuit device as defined in claim 31.

33. The printed circuit board defined in claim 32 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

34. The printed circuit board defined in claim 33 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.