Specialized processing block for programmable logic device

• US 8,266,199 B2
• Filed: 06/05/2006
• Issued: 09/11/2012
• Est. Priority Date: 02/09/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin, Lee, Kwan Yee Martin, Azgomi, Orang, Streicher, Keone, Lin, Yi-Wen
• Primary Examiner(s): Do, Chat
• Assistant Examiner(s): Yaary, Michael D
• Application Number:
  US11/447,472
• Publication Number:
  US 20070185952A1
• Time in Patent Office: 2,290 Days
• Field of Search: 708620-656
• US Class Current: 708/523
• CPC Class Codes: G06F 7/527 in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel G06F7/533 takes precedence
• CPC Class Codes: G06F 7/5272 with row wise addition of partial products
• CPC Class Codes: H03K 19/17732 Macroblocks

Abstract

A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.

Claims

1. A specialized processing block for a programmable logic device, said specialized processing block comprising:

a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators having a respective pair of inputs different from inputs of each other one of said partial product generators and providing a respective plurality of vectors representing a respective partial product of said respective pair of inputs;

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product;

circuitry for shifting said partial products represented by said smaller number of vectors prior to adding them; and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by no fewer than all of said plurality of partial product generators;

wherein;

said circuitry for adding outputs only a sum of all partial products of all of said plurality of partial product generators; and

each said respective partial product is unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products having said different inputs.

2. The specialized processing block of claim 1 further comprising loopback circuitry for feeding back an output of said specialized processing block to an input of said specialized processing block.

3. The specialized processing block of claim 2 wherein said loopback circuitry is used to configure said specialized processing block as an adaptive filter.

4. The specialized processing block of claim 2 further comprising input preprocessing circuitry for aligning inputs from a plurality of sources.

5. The specialized processing block of claim 4 wherein said plurality of sources comprises an input to said specialized processing block and an output of said specialized processing block.

6. The specialized processing block of claim 5 wherein said plurality of sources further comprises an output of another said specialized processing block.

7. The specialized processing block of claim 4 wherein said input preprocessing circuitry comprises registers for registering said inputs.

8. The specialized processing block of claim 7 wherein said registers are chained for inputting data seriatim to each said plurality of multipliers.

9. The specialized processing block of claim 8 wherein said registers comprise an additional register for introducing in said chain delay between groups of said multipliers.

10. The specialized processing block of claim 1 further comprising an output stage, said output stage including:

for each of at least one subset of said specialized processing block, a plurality of adders, said plurality of adders being adaptable to provide as an output one of (a) an output of a multiplication operation involving a plurality of said fundamental processing units, and (b) a sum of (1) a multiplication operation involving at least one of said fundamental processing units and (2) a corresponding output cascaded from another said plurality of adders in another output stage in another one of said specialized processing blocks.

11. The specialized processing block of claim 10 wherein said output stage further comprises feedback circuitry for providing, in cooperation with one of said adders, an accumulation function.

12. The specialized processing block of claim 10 further comprising circuitry for selecting as a shifted output one of a plurality of bit ranges of said block output.

13. The specialized processing block of claim 12 wherein said circuitry for selecting a shifted output comprises a pipeline register stage between said plurality of fundamental units and said output stage.

14. The specialized processing block of claim 12 further comprising circuitry for combining said plurality of bit ranges into a combined output, and circuitry for selecting one of (a) one of said plurality of bit ranges, and (b) said combined output.

15. The specialized processing block of claim 14 wherein said circuitry for combining comprises OR circuitry, wherein said combined output comprises a rotation of said block output.

16. The specialized processing block of claim 10 wherein:

each of said fundamental processing units comprises two multipliers;

said plurality of fundamental processing units comprises at least two said fundamental processing units arranged in groupings of two said fundamental processing units; and

said plurality of adders in said output stage comprises two adders for each said grouping, each of said adders having a first adder width, said two adders being configurable to perform one of (a) a single addition having a width greater than said first adder width to provide said output of said multiplication operation involving said at least two fundamental processing units, and (b) a first addition having a width of at most said first adder width to provide said multiplication operation involving at least one of said fundamental processing units, and a second addition having a width of at most said first adder width to provide said sum of (1) said multiplication operation and (2) said corresponding output cascaded from another said plurality of adders in another output stage in another one of said specialized processing blocks.

17. The specialized processing block of claim 16 further comprising a pipeline register stage between said fundamental processing units and said output stage;

wherein;

said pipeline register stage is adaptable to align data output by said fundamental units to perform said addition having said width greater than said adder width.

18. The specialized processing block of claim 1 further comprising a pipeline register stage between said fundamental processing units and said output stage.

19. A programmable logic device comprising the specialized processing block of claim 1.

20. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 19 coupled to the processing circuitry and the memory.

21. A printed circuit board on which is mounted a programmable logic device as defined in claim 19.

22. The printed circuit board defined in claim 21 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

23. The printed circuit board defined in claim 22 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

24. An integrated circuit device comprising the specialized processing block of claim 1.

25. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

an integrated circuit device as defined in claim 24 coupled to the processing circuitry and the memory.

26. A printed circuit board on which is mounted an integrated circuit device as defined in claim 25.

27. The printed circuit board defined in claim 26 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

28. The printed circuit board defined in claim 27 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.