Multi-level striping and truncation channel-equalization for flash-memory system

• US 8,266,367 B2
• Filed: 05/29/2009
• Issued: 09/11/2012
• Est. Priority Date: 12/02/2003
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Yu, Frank, Lee, Charles C., Ma, Abraham C., Shin, Myeongjin
• Primary Examiner(s): Tsai, Sheng-Jen
• Application Number:
  US12/475,457
• Publication Number:
  US 20090240873A1
• Time in Patent Office: 1,201 Days
• Field of Search: 711/103, 711/E12.001, 711/E12.008
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.

Claims

1. A two-level flash device comprising:

a smart storage switch which comprises;

an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;

a high-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity, which is the size of data that is accessible in parallel, and a scattered capacity, which is the size of data that cannot be accessed in parallel, for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels;

a virtual storage bridge between the smart storage transaction manager and a NVM controller through a LBA bus;

a plurality of NVM controllers, each NVM controller coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge;

a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped;

a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises;

NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the low-level mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data.

2. The two-level flash device of claim 1 wherein the high-level striping mapper further comprises:

a truncation process, activated on power-up, for determining a size of the NVM flash memory in the plurality of flash channels, and for setting a truncation size for all flash channels.

3. The two-level flash device of claim 1 wherein the low-level mapper further comprises:

a bad block table that maps locations of bad blocks in the NVM flash memory controlled by the NVM controller;

wherein the NVM controller reports an available storage capacity to the smart storage switch by subtracting a capacity of the band blocks located by the bad block table.

4. The two-level flash device of claim 1 wherein the LBA bus comprises a Serial AT-Attachment (SATA) bus, a Serial small-computer system interface (SCSI) (SAS) bus, a fiber-channel (FC) bus, an InfiniBand bus, an integrated device electronics (IDE) bus, a Peripheral Components Interconnect Express (PCIe) bus, a compact flash (CF) bus, a Universal-Serial-Bus (USB), a Secure Digital Bus (SD), a MultiMediaCard (MMC), or a LBA bus protocol which transfers read and write commands, a starting page address with a sector offset, and a sector count.

5. The two-level flash device of claim 1 wherein each NVM controller further comprises an error-correction code (ECC) unit for appending page ECC to the host data sent to the assigned flash channel in the plurality of flash channels for storage in the NVM flash memory;

a high-level ECC unit, in the smart storage switch, for generating a stripe ECC from a stripe of the host data generated by the high-level striping mapper;

wherein the stripe ECC is sent to a stripe flash channel plurality of flash channels for storage in the NVM flash memory,

whereby both stripe ECC and page ECC are generated and stored.

6. The two-level flash device of claim 5 wherein the low-level mapper in the NVM controller is a physical to logical map that stores LBA at locations indicating a PBA.

7. The two-level flash device of claim 6 wherein the low-level mapper in the NVM controller further comprises:

a properties table that indicates when a block is a source block, a first shadow block, or a second shadow block;

wherein fresh data from the source block is copied to the second shadow block before the source block is erased and recycled.

8. The two-level flash device of claim 1 further comprising:

an end-of-command flag, stored in a page of the NVM flash memory after host data is stored, the end-of-command flag indicating an end of data for a host command;

a read searcher that reads blocks for the end-of-command flag to locate fresh data.

9. A three-level flash device comprising:

a high-level smart storage switch which comprises;

an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;

a high-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity, which is the size of data that is accessible in parallel, and a scattered capacity, which is the size of data that cannot be accessed in parallel, for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels;

a virtual storage bridge between the smart storage transaction manager and a LBA bus;

a second-level smart storage switch which comprises;

a second upstream interface to the high-level smart storage switch for receiving commands to access NVM and for receiving data and an address from the high-level smart storage switch;

a second-level smart storage transaction manager that manages transactions from NVM devices;

a channel storage processor that maps the address from the high-level smart storage switch to an assigned flash channel to generate a local logical block address (LBA), the channel storage processor performing a mapping to multiple NVM devices attached to the second-level smart storage switch;

a second-level mapper, coupled to the channel storage processor, that stores capacities of all NVM devices for each flash channel;

a plurality of NVM controllers, each NVM controller coupled to the LBA bus to receive the LBA generated by the channel storage processor and the data from the second-level smart storage switch;

a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped;

a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises;

NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the low-level mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data;

wherein the second-level smart storage switch accesses the plurality of flash channels as a stripe of multiple simultaneous accesses of the plurality of flash channel for data stored in the stripe capacity;

wherein the second-level smart storage switch accesses the plurality of flash channels as a single-channel access of one flash channel at a time for data stored in the scattered capacity;

whereby the scattered data is accessed as single-channel access while the striped data is accessed using multiple simultaneous accesses.

10. The three-level flash device of claim 9 wherein the second-level mapper further comprises:

a truncation process, activated on power-up, for determining a selected size of the NVM flash memory, and for setting a selected size of all NVM flash memory.

11. The three-level flash device of claim 9 wherein the high-level striping mapper further comprises:

a truncation process, activated on power-up, for determining a selected size of the plurality of flash channels, and for setting the selected size of all flash channels.

12. The three-level flash device of claim 9 wherein each second-level smart storage switch further comprises:

a channel error-correction code (ECC) unit for generating ECC, the ECC being sent to an assigned NVM flash memory coupled to an assigned NVM controller;

wherein the assigned NVM flash memory is diagonally distributed;

a hamming-code ECC unit, in the second-level smart storage switch, for detecting two-bit errors and for correcting single-bit errors using a hamming-code ECC circuit operating on data read back from the NVM flash memory;

wherein the ECC is sent to a redundant channel for storage in the NVM flash memory,

whereby stripe ECC are generated and stored.

13. The three-level flash device of claim 9 wherein the high-level storage smart switch further comprises:

a high-level error-correction code (ECC) unit for appending channel ECC to data sent to the assigned flash channels, wherein the channel ECC is stored in the NVM flash memory;

wherein the assigned flash channels storing the channel ECC are diagonally distributed;

a hamming-code ECC unit, in the high-level smart storage switch, for generating a stripe ECC from a stripe of the host data, wherein the stripe is generated by the high-level striping mapper;

wherein the stripe ECC is sent to a stripe channel for storage in the NVM flash memory,

whereby both stripe ECC and page ECC are generated and stored.

14. The three-level flash device of claim 9 wherein the high-level smart storage transaction manager further comprises:

an interleave unit, coupled to the virtual storage bridge, for interleaving host data to a plurality of interleaves of the plurality of flash channels attached to the NVM flash memory,

whereby the plurality of flash channels are accessed in interleaves.

15. The three-level flash device of claim 9 wherein the second-level smart storage transaction manager further comprises:

an interleave unit, coupled to a virtual storage bridge of the second-level smart storage switch, for interleaving striped data to a plurality of interleaves of the plurality of channels attached to the NVM flash memory,

whereby the plurality of NVM controllers are accessed in interleaves.

16. The three-level flash device of claim 9 wherein the high-level smart storage transaction manager further comprises:

a multi-channel parallel accessing unit, coupled to the virtual storage bridge, for parallel access of host data to a plurality of channels attached to a plurality of the second-level smart storage switch,

whereby the plurality of the second-level smart storage switch are accessed in parallel.

17. The three-level flash device of claim 9 wherein the second-level smart storage transaction manager further comprises:

a multi-channel parallel accessing unit, coupled to a virtual storage bridge of second-level smart storage switch, for parallel access of striped data to a plurality of NVM controllers,

whereby the plurality of NVM controllers are accessed in parallel.

18. The three-level flash device of claim 9 wherein the high-level smart storage switch further comprises:

a volatile memory buffer for temporarily storing host data in a volatile memory that loses data when power is disconnected;

a caching circuit, implemented by the volatile memory buffer, for storing associated buffer data from the upstream interface, the caching circuit for transaction buffering;

wherein the second-level smart storage switch further comprises;

second-level cache means for caching data in the plurality of NVM controllers,

wherein the NVM controller further comprises;

low-level cache means for caching data in the NVM flash memory.

19. A smart storage switch two-level controller comprising:

a smart storage switch which comprises;

an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;

a first-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity, which is the size of data that is accessible in parallel, and a scattered capacity, which is the size of data that cannot be accessed in parallel, for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels;

a virtual storage bridge between the smart storage transaction manager and a NVM controller through a LBA bus;

a volatile memory buffer for temporarily storing host data in a volatile memory that loses data when power is disconnected;

a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge;

a low-level volatile memory buffer, coupled to the NVM controller, for buffering data; and

a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped.

20. A smart storage switch three-level controller comprising:

a first-level smart storage switch which comprises;

an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;

a first-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity, which is the size of data that is accessible in parallel, and a scattered capacity, which is the size of data that cannot be accessed in parallel, for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels;

a virtual storage bridge between the smart storage transaction manager and a LBA bus;

a volatile memory buffer for temporarily storing host data in a volatile memory that loses data when power is disconnected;

a second-level smart storage switch which comprises;

a second upstream interface to the first-level smart storage switch for receiving commands to access NVM and for receiving data and an address from the first-level smart storage switch;

a second-level smart storage transaction manager that manages transactions from the NVM devices;

a second-level stripping mapper, coupled to the channel storage processor, that stores capacities of all NVM devices for each flash channel;

a channel storage processor that maps the address from the first-level smart storage switch to an assigned flash channel to generate a local logical block address (LBA), the channel storage processor performing a mapping to multiple NVM devices attached to the second-level smart storage switch;

a NVM controller, coupled to the LBA bus to receive the LBA generated by the channel storage processor and the data from the second-level smart storage switch;

a low-level volatile memory buffer, coupled to the NVM controller, for buffering data; and

a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped.

21. A smart storage switch three-level controller comprising:

a first-level smart storage switch which comprises;

an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;

a first-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity, which is the size of data that is accessible in parallel, and a scattered capacity, which is the size of data that cannot be accessed in parallel, for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels;

a virtual storage bridge between the smart storage transaction manager and a LBA bus;

a second-level smart storage switch which comprises;

a second upstream interface to the first-level smart storage switch for receiving commands to access NVM and for receiving data and an address from the first-level smart storage switch;

a second-level smart storage transaction manager that manages transactions from the NVM devices;

a second-level stripping mapper, coupled to the channel storage processor, that stores capacities of all NVM devices for each flash channel;

a channel storage processor that maps the address from the first-level smart storage switch to an assigned flash channel to generate a local logical block address (LBA), the channel storage processor performing a mapping to multiple NVM devices attached to the second-level smart storage switch.