High bandwidth memory interface
First Claim
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1. A Dynamic Random Access Memory (DRAM) controller configured for communication with at least one semiconductor device over an interface, the DRAM controller comprising:
- a) data terminals for coupling to the interface and for providing data signals for transmission to the semiconductor device;
b) at least one data clock terminal for coupling to the interface and for providing at least one aperiodic data clock signal for transmission to the semiconductor device;
c) data output drivers for driving said data signals on said data terminals;
d) at least one clock driver for driving said at least one aperiodic data clock signal on said at least one data clock terminal; and
e) resistive termination devices within said DRAM controller and coupled to each of said data and data clock terminals, and said resistive termination devices being integrated with said DRAM controller on a semiconductor chip.
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Abstract
A DRAM system configured for high bandwidth communication, the system includes at least one DRAM having resistive termination devices within the DRAM, and a controller connected to the DRAM through a data bus. The controller includes resistive termination devices and the data bus includes at least one clock line driven intermittently. The data bus provides write data from the controller to the DRAM, and provides read data from the DRAM to the controller.
33 Citations
43 Claims
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1. A Dynamic Random Access Memory (DRAM) controller configured for communication with at least one semiconductor device over an interface, the DRAM controller comprising:
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a) data terminals for coupling to the interface and for providing data signals for transmission to the semiconductor device; b) at least one data clock terminal for coupling to the interface and for providing at least one aperiodic data clock signal for transmission to the semiconductor device; c) data output drivers for driving said data signals on said data terminals; d) at least one clock driver for driving said at least one aperiodic data clock signal on said at least one data clock terminal; and e) resistive termination devices within said DRAM controller and coupled to each of said data and data clock terminals, and said resistive termination devices being integrated with said DRAM controller on a semiconductor chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A Dynamic Random Access Memory (DRAM) system comprising:
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a) at least one DRAM including resistive termination devices within said at least one DRAM and integrated with said at least one DRAM on a semiconductor chip; b) a DRAM controller; and c) a data bus having said resistive termination devices coupled to it, said data bus for providing write data from said DRAM controller to said DRAM, and for providing read data from said DRAM to said DRAM controller, the data bus including at least one data clock line that is driven with an aperiodic data clock signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A Dynamic Random Access Memory (DRAM) comprising:
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a) a first terminal for coupling to a clock line; b) a plurality of second terminals for coupling to a command bus providing address and control information to the DRAM, said clock line and said command bus comprising a source synchronous bus; c) resistive termination devices within the DRAM and coupled to said plurality of second terminals, and said resistive termination devices being integrated with the DRAM on a single chip; and d) at least one third terminal for coupling to at least one data clock line that is driven with an aperiodic data clock signal. - View Dependent Claims (26, 27, 28)
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29. A Dynamic Random Access Memory (DRAM) system comprising:
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a) at least one DRAM including output drivers; b) a DRAM controller including output drivers; c) a bidirectional data bus for providing write data from said at least one DRAM controller to said at least one DRAM, and for providing read data from said at least one DRAM to said DRAM controller, said drivers of said DRAM controller and said at least one DRAM for driving write and read data, respectively, onto said data bus, and said data bus including at least one data clock line that is driven with an aperiodic data clock signal; and d) resistive termination devices located within said at least one DRAM and coupled to said data bus, and said resistive termination devices being integrated with said at least one DRAM on a single chip. - View Dependent Claims (30, 31)
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32. In a Dynamic Random Access Memory (DRAM) controller, a method for synchronization comprising:
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a) resistively terminating data bus terminals and data clock terminals of the DRAM controller with termination resistors integrated with said DRAM controller on a semiconductor chip; b) receiving aperiodic data clock signals on said data clock terminals; c) generating a data sampling clock with said aperiodic data clock signals; d) receiving read data signals on said data bus terminals; and e) sampling the received read data signals with said data sampling clock so that the data input to the device is synchronized with the aperiodic data clock signals. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
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Specification