Integrated circuit with interpolation to avoid harmonic interference

• US 8,266,468 B2
• Filed: 10/06/2010
• Issued: 09/11/2012
• Est. Priority Date: 07/26/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Behzad, Arya Reza, Gonikberg, Mark, Rofougaran, Ahmadreza (Reza)
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US12/899,256
• Publication Number:
  US 20110022875A1
• Time in Patent Office: 706 Days
• Field of Search: 713/500, 713/600, 331/1.R, 331/46, 326/93, 327/100, 375/316, 375/354, 455/130
• US Class Current: 713/500
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 15/06 by local oscillators of receivers
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics
• CPC Class Codes: H04B 2215/068 by avoiding a reception frequency range
• CPC Class Codes: H04L 27/0014 Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.

Claims

1. A circuit comprises:

a clock circuit for producing a digital clock signal; and

processing circuitry clocked by the digital clock signal and operating to;

receive data at a nominal digital clock rate of the digital clock signal;

process, at an adjusted digital clock rate of the digital clock signal, the data to produce processed data having a rate corresponding to the nominal digital clock rate; and

interpolate, at an interpolation rate of the digital clock signal, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate;

wherein harmonic components of the digital clock signal having the adjusted digital clock rate do not interfere with the operation of at least a portion of the circuit.

2. The circuit of claim 1, further comprising:

a processing module operating to;

determine that the harmonic component of the digital clock signal interferes with the operation of the at least a portion of the circuit by determining whether the harmonic component of the digital clock signal is within a frequency passband; and

when the harmonic component of the digital clock signal is within the frequency passband, provide an indication to the clock circuit to adjust the rate of the digital clock signal from the nominal digital clock rate to the adjusted digital clock rate, wherein harmonic components of the digital clock signal having the adjusted digital clock rate are outside of the frequency passband.

3. The circuit of claim 2, wherein the processing circuitry comprises:

a digital modulation module operating to modulate, at the adjusted digital clock rate, the data at the nominal digital clock rate to produce modulated data having a rate corresponding to the nominal digital clock rate;

an interpolation module operating to interpolate, at the interpolation rate, the modulated data to produce interpolated modulated data having a rate corresponding to the interpolation rate; and

a digital to analog conversion module operating to convert the interpolated modulated data into analog modulated data, wherein a digital portion of the digital to analog conversion module is clocked in accordance with the interpolation rate.

4. The circuit of claim 3, wherein the digital modulation module comprises:

digital modulation circuitry operating to modulate, at the adjusted digital clock rate, the data to produce modulated data having a rate corresponding to the adjusted digital clock rate; and

rate adjusting circuitry operating to convert the modulated data having the rate corresponding to the adjusted digital clock rate into the modulated data having the nominal digital clock rate.

5. The circuit of claim 3 further comprises:

an analog filter module operating to filter the analog modulated data to produce filtered modulated data;

an up-conversion module operating to convert the filtered modulated data into an upconverted signal;

a power amplifier module operating to amplify the up-converted signal to produce a transmit radio frequency (RF) signal having a carrier frequency within the frequency passband; and

an RF filtering module operating to filter the transmit RF signal to produce an outbound RF signal.

6. The circuit of claim 1 comprises:

the clock circuit operating to produce a second digital clock signal at the interpolation rate, wherein harmonic components of the second digital clock signal having the interpolation rate do not interfere with the operation of the at least a portion of the circuit.

7. The circuit of claim 1 comprises:

the adjusted digital clock rate is at a higher rate than the nominal digital clock rate.

8. The circuit of claim 1 comprises:

the interpolation rate corresponding to the adjusted digital clock rate.

9. The circuit of claim 1 comprises:

an integrated circuit (IC) substrate that supports the clock circuit and the processing circuitry.

10. A circuit comprises:

a clock circuit operating to produce a digital clock signal; and

processing circuitry clocked at the digital clock signal and operating to;

receive data at an interpolation rate of the digital clock signal;

interpolate, in accordance with the interpolation rate, the data to produce interpolated data having a rate corresponding to a nominal digital clock rate of the digital clock signal; and

process, in accordance with an adjusted digital clock rate of the digital clock signal, the interpolated data to produce processed data having a rate corresponding to the nominal digital clock rate;

wherein harmonic components of the digital clock signal having the adjusted digital clock rate do not interfere with the operation of the at least a portion of the circuit.

11. The circuit of claim 10, further comprising:

a processing module operating to;

determine that the harmonic component of the digital clock signal interferes with the operation of the at least a portion of the circuit by determining whether the harmonic component of the digital clock signal is within a frequency passband; and

when the harmonic component of the digital clock signal is within the frequency passband, provide an indication to the clock circuit to adjust the rate of the digital clock signal from the nominal digital clock rate to the adjusted digital clock rate, wherein harmonic components of the digital clock signal having the adjusted digital clock rate are outside of the frequency passband.

12. The circuit of claim 11, wherein the processing circuitry comprises:

an analog to digital conversion module operating to convert analog modulated data into the data at the interpolation rate, wherein a digital portion of the analog to digital conversion module is clocked in accordance with the interpolation rate;

an interpolation module operating to interpolate, at the interpolation rate, the data at the interpolation rate to produce interpolated modulated data having a rate corresponding to the nominal digital clock rate; and

a digital demodulation module operating to demodulate, at the adjusted digital clock rate, the interpolated modulated data at the nominal digital clock rate to produce recovered data having a rate corresponding to the nominal digital clock rate.

13. The circuit of claim 12, wherein the digital demodulation module comprises:

digital demodulation circuitry coupled to demodulate, at the adjusted digital clock rate, the interpolated modulated data to produce demodulated data having a rate corresponding to the adjusted digital clock rate; and

rate adjusting circuitry coupled to convert the demodulated data having the rate corresponding to the adjusted digital clock rate into the recovered data having the nominal digital clock rate.

14. The circuit of claim 12, wherein the interpolation module comprises:

sampling circuitry to sample the data at the interpolation rate to produce sampled data; and

rate adjusting circuitry operating to convert the sampled data into the interpolated modulated data having the rate corresponding to the nominal digital clock rate.

15. The circuit of claim 12 further comprises:

a radio frequency (RF) filtering module operating to filter an inbound RF signal to produce a filtered inbound RF signal;

a low noise amplifier module operating to amplify the filtered inbound RF signal to produce an amplified inbound RF signal having a carrier frequency within the frequency passband;

an down-conversion module operating to convert the amplified inbound RF signal into modulated data; and

an analog filter module operating to filter the modulated data to produce the analog modulated data.

16. The circuit of claim 10 comprises:

the clock circuit coupled to produce a second digital clock signal, wherein harmonic components of the second digital clock signal having the interpolation rate do not interfere with the operation of the at least a portion of the circuit,

not interfere with the operation of at least a portion of the circuit.

17. The circuit of claim 10 comprises:

the interpolation rate corresponding to the adjusted digital clock rate.

18. The circuit of claim 10 comprises:

the adjusted digital clock rate is at a higher rate than the nominal digital clock rate.

19. The circuit of claim 10 comprises:

an integrated circuit (IC) substrate that supports the clock circuit and the processing circuitry.

20. A radio frequency (RF) circuit comprises:

a clock circuit for producing a digital clock signal;

a transmitter section for converting an analog outbound symbol stream into an outbound RF signal;

a digital to analog conversion module for converting a digital outbound symbol stream into the analog outbound symbol stream; and

processing circuitry clocked by the digital clock signal and operating to;

receive outbound data at a nominal digital clock rate of the digital clock signal;

modulate, at an adjusted digital clock rate of the digital clock signal, the outbound data to produce modulated outbound data having a rate corresponding to the nominal digital clock rate; and

interpolate, at an interpolation rate of the digital clock signal, the modulated outbound data to produce the digital outbound symbol stream having a rate corresponding to the interpolation rate;

wherein harmonic components of the digital clock signal having the adjusted digital clock rate do not interfere with the operation of at least a portion of the RF circuit.