Stripe based memory operation

• US 8,266,501 B2
• Filed: 09/29/2009
• Issued: 09/11/2012
• Est. Priority Date: 09/29/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): TRIMMINGS, JOHN P
• Application Number:
  US12/569,412
• Publication Number:
  US 20110078496A1
• Time in Patent Office: 1,078 Days
• Field of Search: None
• US Class Current: 714/769
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/1028 Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.

Claims

1. A method for stripe-based memory operation, comprising:

writing data in a first stripe having a particular stripe size and being across a storage volume of a plurality of memory devices;

updating a portion of the first stripe including;

writing updated data in a portion of a second stripe, the second stripe having the particular stripe size and being across the storage volume of the plurality of memory devices; and

invalidating the portion of the first stripe; and

maintaining the invalid portion of the first stripe and a remainder of the first stripe until the first stripe is reclaimed.

2. The method of claim 1, wherein writing data in the first stripe includes splitting write data into a number of fragments and writing the number of fragments to the plurality of memory devices.

3. The method of claim 2, wherein writing the number of fragments to the plurality of memory devices includes writing at least one fragment to each of the plurality of memory devices.

4. The method of claim 2, wherein writing the number of fragments to the plurality of memory devices includes writing at least one fragment to each of a subset of the plurality of memory devices.

5. The method of claim 4, wherein writing at least one fragment to each of a subset of the plurality of memory devices includes writing a respective page of the write data to each of a subset of the plurality of memory devices.

6. The method of claim 1, wherein updating the portion of the first stripe includes writing updated data in the portion of the second stripe without reading or copying the data written in the first stripe.

7. The method of claim 1, wherein:

writing data in the first stripe includes writing data associated with a number of logical block addresses (LBAs); and

updating the portion of the first stripe includes writing updated data associated with at least one of the number of LBAs.

8. The method of claim 1, wherein maintaining the first stripe includes preventing erasing of the first stripe.

9. The method of claim 1, wherein maintaining the first stripe includes reading at least a portion of the remainder of the first stripe.

10. The method of claim 1, further comprising reclaiming the first stripe.

11. The method of claim 10, wherein reclaiming the first stripe includes:

copying the remainder of the first stripe to a third stripe in response to a wear leveling operation; and

erasing the first stripe.

12. The method of claim 1, further comprising reading the portion of the second stripe on a page basis without reading the remainder of the first stripe or another portion of the second stripe.

13. A method for stripe-based memory operation, comprising:

writing original data in a first stripe across a storage volume of a plurality of memory devices;

updating at least a fragment of the written original data, wherein updating includes writing updated data in a second stripe without reading or copying the written original data; and

wherein the method includes writing unrelated data in the second stripe concurrent with writing the updated data in the second stripe, wherein the unrelated data is unrelated to the original data in the first stripe and the updated data in the second stripe.

14. The method of claim 13, wherein:

writing original data includes writing original data associated with a number of logical block addresses (LBAs); and

updating at least the fragment of the original data includes writing updated data associated with at least one of the number of LBAs.

15. The method of claim 13, wherein the method further includes:

calculating respective first level error correction data based on each fragment of the original data; and

calculating second level error correction data based on the original data;

wherein writing the original data includes writing the original data and the first level error correction data in a first subset of the plurality of memory devices, and writing the second level error correction data in a second subset of the plurality of memory devices.

16. The method of claim 15, wherein the method includes detecting an error in a fragment of the original data in the first stripe and correcting the error with the first level error correction data.

17. The method of claim 15, wherein the method includes:

detecting an error in a fragment of original data in the first stripe, wherein the error is uncorrectable with the first level error correction data; and

correcting the error, wherein correcting the error includes;

creating replacement data for the fragment of original data based on at least a remainder of the original data and the second level error correction data in the first stripe; and

writing the replacement data in a third stripe without writing the remainder of the original data in the third stripe.

18. The method of claim 17, wherein the method includes writing unrelated data in the third stripe concurrent with writing the replacement data in the third stripe, wherein the unrelated data is unrelated to the original data in the first stripe or the replacement data in the third stripe.

19. The method of claim 15, wherein the second level error correction data comprises parity data.

20. The method of claim 13, wherein the method includes reading a fragment of non-updated original data without reading a remainder of the original data.

21. A method for stripe-based memory operation, comprising:

writing data in a stripe across a storage volume of a plurality of memory devices;

detecting an error associated with a portion of the stripe;

effectively removing the portion of the stripe from the stripe in response to detecting the error; and

operating the stripe without the removed portion.

22. The method of claim 21, wherein operating the stripe without the removed portion includes subsequently writing data in the stripe across the storage volume of the plurality of memory devices without writing data in the removed portion.

23. The method of claim 21, wherein writing data in the stripe includes writing first level error correction data with the data.

24. The method of claim 23, wherein detecting an error associated with the portion of the stripe includes detecting an error that is correctable using the first level error correction data;

and

wherein the method includes correcting the error with the first level error correction data.

25. The method of claim 23, further comprising writing second level data in the stripe;

and

wherein detecting an error associated with the portion of the stripe includes detecting an error that is not correctable using the first level error correction data; and

wherein the method includes creating replacement data for data associated with the removed portion of the stripe based on a remainder of the data and the second level error correction data.

26. The method of claim 25, wherein the method includes writing the replacement data in an additional stripe without writing the remainder of the data in the additional stripe.

27. The method of claim 25, wherein the method includes effectively removing the portion of the stripe from the stripe in response to detecting the error that is not correctable using the first level error correction data.

28. The method of claim 21, wherein removing the portion of the stripe includes providing an indication in a block table that the portion is invalid.

29. Memory system control circuitry, comprising:

non-volatile memory control circuitry configured to;

write original data associated with a plurality of addresses in a first stripe across a plurality of channels;

write updated data associated with at least one of the plurality of addresses in a second stripe across the plurality of channels without reading or copying the original data in the first stripe; and

write unrelated data in the second stripe concurrent with writing the updated data in the second stripe, wherein the unrelated data is unrelated to the original data in the first stripe and the updated data in the second stripe.

30. The memory system control circuitry of claim 29, further comprising:

a switch coupled to the non-volatile memory control circuitry; and

host interface circuitry coupled to the switch and configured to;

receive the original data; and

receive the updated data.

31. The memory system control circuitry of claim 30, wherein:

the host interface control circuitry is coupled to the switch across host-memory translation circuitry; and

the host-memory translation circuitry is configured to translate the plurality of addresses from host addresses to memory addresses.

32. The memory system control circuitry of claim 31, wherein a logical memory address associated with the original data is the same as a logical memory address associated with the updated data.

33. The memory system control circuitry of claim 29, wherein:

the non-volatile memory control circuitry includes discrete channel memory control circuitry for each of the plurality of channels; and

the non-volatile memory control circuitry is configured to operate a plurality of non-volatile memory devices associated with the plurality of channels as a striped redundant array of independent disks (RAID).

34. The memory system of claim 33, wherein the non-volatile memory control circuitry is configured to operate the striped RAID with a programmable stripe size such that a number of non-volatile memory devices included in the stripe is programmable.

35. The memory system of claim 33, wherein the non-volatile memory control circuitry is configured to operate the striped RAID with a programmable RAID structure such that a particular RAID storage scheme to be implemented is programmable.

36. The memory system control circuitry of claim 35, wherein the non-volatile memory control circuitry is configured to operate one of the plurality of channels as a parity channel.

37. The memory system control circuitry of claim 36, further comprising an exclusive or (XOR) circuit configured to calculate parity data based on the original data.

38. Memory system control circuitry, comprising:

non-volatile memory control circuitry configured to;

write received data in a stripe across a plurality of channels; and

detect an error associated with a portion of the stripe; and

memory management circuitry configured to effectively remove the portion of the stripe from the stripe in response to the non-volatile memory control circuitry detecting the error;

wherein the non-volatile memory control circuitry is further configured to operate the stripe without the removed portion of the stripe.

39. The memory system control circuitry of claim 38, wherein the portion of the stripe comprises one of the group of portions including a memory device, a die, a block, a page, and a sector.

40. The memory system control circuitry of claim 38, further comprising a switch and host interface circuitry, wherein the non-volatile memory control circuitry is coupled to the switch, wherein:

the host interface control circuitry is coupled to the switch via host-memory translation circuitry, wherein;

the host-memory translation circuitry includes an exclusive or (XOR) circuit configured to calculate second level error correction data based on the original data, and wherein;

the non-volatile memory control circuitry is configured to write the original data and the second level error correction data in the stripe across the plurality of channels substantially simultaneously.

41. The memory system control circuitry of claim 40, wherein the non-volatile memory control circuitry is configured to write the second level error correction data in the stripe across one of the plurality of channels and to write the original data in the stripe across a remainder of the plurality of channels.

42. The memory system control circuitry of claim 38, wherein:

the non-volatile memory control circuitry includes error detection/correction circuitry, wherein the error detection/correction circuitry is configured to;

calculate first level error correction data for fragments of the original data; and

detect errors in fragments of data read from the stripe; and

the non-volatile memory control circuitry is configured to write the first level error correction data with the original data in the stripe across the plurality of channels.

43. The memory system control circuitry of claim 38, wherein the non-volatile control circuitry is configured to read portions of the stripe on a page-basis without reading a remainder of the stripe.

44. The memory system control circuitry of claim 38, wherein the memory management circuitry is configured to:

indicate the portion of the stripe as invalid in a block table; and

update a logical block address (LBA) table with a new physical address for at least one LBA previously associated with the portion of the stripe.

45. A memory system, comprising:

control circuitry; and

a plurality of solid state memory devices, wherein;

each of the plurality of solid state memory devices is coupled to the control circuitry by a respective one of a plurality of channels; and

the plurality of solid state memory devices provide a storage volume for the memory system;

wherein the control circuitry is configured to;

write data in a stripe across the storage volume of the plurality of solid state memory devices across the plurality of channels;

read data from a portion of the stripe across one of the plurality of channels; and

reclaim portions of the storage volume on a stripe-basis in response to one or more of the group including;

all portions of the particular stripe having an invalid indication in the block table; and

a garbage collection threshold amount of portions of the particular stripe having an invalid indication in the block table, wherein the threshold amount of portions is greater than one and less than all portions.

46. The memory system of claim 45, wherein the control circuitry is configured to:

maintain a block table with information regarding validity of portions of the stripe;

indicate that a portion of the stripe is invalid in the block table in response to updated data corresponding to the portion of the stripe being written to another stripe; and

operate the stripe without the invalid portion.

47. The memory system of claim 46, wherein:

the memory system includes a volatile memory; and

the block table is stored in the volatile memory.

48. The memory system of claim 47, wherein a copy of the block table is stored in at least one of the plurality of solid state memory devices.

49. The memory system of claim 45, wherein the control circuitry includes discrete channel memory control circuitry for each of the plurality of channels.

50. The memory system of claim 45, wherein:

the control circuitry comprises an application specific integrated circuit (ASIC);

the plurality of solid state memory devices comprise NAND flash chips; and

the memory system comprises a solid state drive (SSD).

51. The memory system of claim 45, wherein the stripe comprises portions of the plurality of solid state memory devices that store the data written in the stripe.

52. A method for stripe-based memory operation, comprising:

writing original data in a first stripe across a storage volume of a plurality of memory devices;

updating at least a fragment of the written original data, wherein updating includes writing updated data in a second stripe without reading or copying the written original data;

calculating respective first level error correction data based on each fragment of the original data;

calculating second level error correction data based on the original data;

wherein writing the original data includes writing the original data and the first level error correction data in a first subset of the plurality of memory devices, and writing the second level error correction data in a second subset of the plurality of memory devices;

detecting an error in a fragment of original data in the first stripe, wherein the error is uncorrectable with the first level error correction data; and

correcting the error, wherein correcting the error includes;

creating replacement data for the fragment of original data based on at least a remainder of the original data and the second level error correction data in the first stripe; and

writing the replacement data in a third stripe without writing the remainder of the original data in the third stripe.

53. The method of claim 52, wherein the method includes writing unrelated data in the second stripe concurrent with writing the updated data in the second stripe, wherein the unrelated data is unrelated to the original data in the first stripe and the updated data in the second stripe.

54. A memory system, comprising:

control circuitry;

a volatile memory coupled to the control circuitry and storing a block table;

a plurality of solid state memory devices, wherein;

each of the plurality of solid state memory devices is coupled to the control circuitry by a respective one of a plurality of channels;

the plurality of solid state memory devices provide a storage volume for the memory system; and

a copy of the block table is stored in at least one of the plurality of solid state memory devices;

wherein the control circuitry is configured to;

write data in a stripe across the storage volume of the plurality of solid state memory devices across the plurality of channels;

read data from a portion of the stripe across one of the plurality of channels;

reclaim portions of the storage volume on a stripe-basis;

maintain a block table with information regarding validity of portions of the stripe;

indicate that a portion of the stripe is invalid in the block table in response to updated data corresponding to the portion of the stripe being written to another stripe; and

operate the stripe without the invalid portion.

55. The memory system of claim 54, wherein the control circuitry is configured to reclaim a particular stripe in response to one or more of the group including:

all portions of the particular stripe having an invalid indication in the block table; and

a garbage collection threshold amount of portions of the particular stripe having an invalid indication in the block table.