Apparatus, system, and method for using multi-level cell storage in a single-level cell mode
First Claim
1. A method for storing data in an electronic memory device, the method comprising:
- receiving a write command to write data to an electronic memory device having multi-level cell (MLC) memory elements, wherein each MLC memory element is programmable to designated programming states, wherein each designated programming state is representative of at least two bits of data; and
programming at least one of the MLC memory elements to one of a plurality of restricted programming states in a single-level cell (SLC) mode, wherein the restricted programming states exclude at least one of the designated programming states, and the restricted programming states comprise;
a first state which is an erase state; and
a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements.
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Abstract
A controller is used for an electronic memory device which has multi-level cell (MLC) memory elements. Each MLC memory element is capable of storing at least two bits. The controller includes a physical interface to couple the controller to the electronic memory device. The controller also includes a processing unit coupled to the physical interface. The processing unit operates the electronic memory device in a single-level cell (SLC) mode using a restricted number of programming states for a single data bit. The restricted number of programming states includes a first state which is an erase state. The restricted number of programming states also includes a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements.
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Citations
20 Claims
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1. A method for storing data in an electronic memory device, the method comprising:
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receiving a write command to write data to an electronic memory device having multi-level cell (MLC) memory elements, wherein each MLC memory element is programmable to designated programming states, wherein each designated programming state is representative of at least two bits of data; and programming at least one of the MLC memory elements to one of a plurality of restricted programming states in a single-level cell (SLC) mode, wherein the restricted programming states exclude at least one of the designated programming states, and the restricted programming states comprise; a first state which is an erase state; and a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A computer program product, comprising:
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a computer readable storage device to store a computer readable program, wherein the computer readable program, when executed by a processor within a computer, causes the computer to perform operations for storing data in an electronic memory device, the operations comprising; receiving a write command to write the data to an electronic memory device having multi-level cell (MLC) memory elements, wherein each MLC memory element is programmable to 2^X designated programming states, wherein each designated programming state is representative of X bits of data, where X>
1; andprogramming at least one of the MLC memory elements to one of a plurality of restricted programming states in a reduced-level cell (RLC) mode to represent Y bits of the data, where Y<
X, wherein the restricted programming states exclude at least one of the designated programming states, and the restricted programming states comprise;a first state which is an erase state; and a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A controller for an electronic memory device having multi-level cell (MLC) memory elements, wherein each MLC memory element is capable of storing at least two data bits, the controller comprising:
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a physical interface to couple the controller to the electronic memory device; and a processing unit coupled to the physical interface, the processing unit to operate the electronic memory device in a single-level cell (SLC) mode using a restricted number of programming states for a single data bit, wherein the restricted number of programming states comprise; a first state which is an erase state; and a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements. - View Dependent Claims (20)
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Specification