Silicon based solid state lighting

• US 8,268,648 B2
• Filed: 08/06/2009
• Issued: 09/18/2012
• Est. Priority Date: 06/12/2007
• Status: Active Grant

• Current Assignee: Siphoton Incorporated
• Original Assignee: Siphoton Incorporated
• Inventors: Pan, Shaoher X.
• Primary Examiner(s): Vu, Hung
• Application Number:
  US12/537,102
• Publication Number:
  US 20090298212A1
• Time in Patent Office: 1,139 Days
• Field of Search: 438/22, 438/29, 438/46, 438/47, 438/962, 257/627, 257/E33.003, 257/E33.005, 257/E33.007, 257/E33.008, 257/E33.023, 257/E33.025
• US Class Current: 438/22
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01S 2301/173 The laser chip comprising special buffer layers, e.g. dislocation prevention or reduction
• CPC Class Codes: H01S 5/34333 with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A semiconductor device includes a substrate comprising a first surface having a [111] orientation and a second surface having a second orientation and a plurality of III-V compound layers on the substrate, wherein the plurality of III-V compound layers are configured to emit light when an electric current is produced in one or more of the plurality of III-V compound layers.

Claims

1. A method comprising:

forming a trench on a silicon semiconductor substrate, the substrate having a first surface along the (100) crystal plane and the trench having a second surface that is not parallel with the first surface of the substrate, the second surface formed along the (111) crystal plane;

forming a buffer layer on, conforming with and parallel with a substantial portion of the second surface while leaving the first surface along the (100) crystal plane substantially free of buffer material;

forming a first III-V compound layer on, conforming with and parallel with a substantial portion of the buffer layer;

forming a quantum-well layer on, conforming with and parallel with a substantial portion of the first III-V compound layer, wherein the quantum-well layer is configured to emit light when an electric current is produced in the quantum-well layer; and

forming a second III-V compound layer on, conforming with and parallel with at least a substantial portion of the quantum-well layer.

2. The method of claim 1, wherein the buffer layer is formed by atomic layer deposition (ALD), Metal Organic Chemical Vapor Deposition (MOCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Chemical Vapor Deposition (CVD), or Physical vapor deposition (PVD).

3. The method of claim 1, wherein the buffer layer is formed on the substrate at a temperature in a range of 450°

C. to 1050°

C.

4. The method of claim 3, wherein the buffer layer comprises a material selected from the group consisting of GaN, ZnO, AlN, HfN, AlAs, SiCN, TaN, SiC and combinations of these.

5. The method of claim 1, further comprising:

forming a first electrode on the first III-V compound layer; and

forming a second electrode on the second III-V compound layer.