Diode array and method of making thereof

• US 8,268,678 B2
• Filed: 11/18/2010
• Issued: 09/18/2012
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Maxwell, Steven, Konevecki, Michael, Clark, Mark H., Raghuram, Usha
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): PATHAK, SHANTANU
• Application Number:
  US12/949,056
• Publication Number:
  US 20110065243A1
• Time in Patent Office: 670 Days
• Field of Search: None
• US Class Current: 438/131
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface.

Claims

1. A method of making a non-volatile memory device, comprising:

providing a substrate having a substrate surface; and

forming a non-volatile memory array over the substrate surface;

wherein;

the non-volatile memory array comprises an array of semiconductor diodes; and

each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface; and

forming at least one pillar conductor which is disposed vertically with respect to the substrate surface and which contacts first conductivity type regions of the diodes of the array of semiconductor diodes; and

forming a plurality of horizontal conductors which are disposed horizontally in the plurality of device levels with respect to the substrate surface and which contact second conductivity type regions of the diodes of the array of semiconductor diodes;

wherein;

the horizontal conductors extend to a different distance in a stepped configuration such that a portion of each horizontal conductor is exposed below an adjacent overlying horizontal conductor; and

one of a plurality of separate electrical connectors contacts each exposed portion of each horizontal conductor.

2. The method of claim 1, wherein:

each semiconductor diode is disposed horizontally with respect to the substrate surface; and

in each semiconductor diode, the first conductivity type region comprises a p-type semiconductor region, the second conductivity type region comprises an n-type semiconductor region, and the p-type semiconductor region and the n-type semiconductor region are equidistant from the substrate surface.

3. The method of claim 2, wherein each non-volatile memory device of the non-volatile memory array comprises an antifuse dielectric disposed in series with one semiconductor diode from the array of semiconductor diodes.

4. The method of claim 2, wherein:

each non-volatile memory device of the non-volatile memory array consists essentially of one semiconductor diode from the array of semiconductor diodes; and

in operation, the semiconductor diode is adapted to change its resistivity state in response to an external voltage pulse to write or erase a data bit.

5. The method of claim 2, wherein the step of forming the non-volatile memory array comprises monolithically forming a plurality of device levels of the semiconductor diodes such that the plurality of device levels are stacked in a vertical direction with respect to the substrate surface.