Independently accessed double-gate and tri-gate transistors in same process flow

• US 8,268,709 B2
• Filed: 08/06/2010
• Issued: 09/18/2012
• Est. Priority Date: 09/29/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chang, Peter L. D., Doyle, Brian S.
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US12/852,408
• Publication Number:
  US 20100297838A1
• Time in Patent Office: 774 Days
• Field of Search: 438/283, 438/275, 438/221, 438/347, 438/585, 438/599
• US Class Current: 438/585
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.

Claims

1. A method comprising:

forming a first transistor on a substrate having a first body surrounded on three sides by a first metal gate; and

forming a second transistor on the substrate having a second body having two independent metal gates on opposite sides of the second body, and an insulative member formed on the second body, the insulative member formed between the two independent metal gates, wherein the first and second transistors are formed in a same process flow.

2. The method of claim 1 wherein same process steps are used to form the bodies, the metal gates, and gate dielectrics of the two transistors.

3. The method of claim 1 wherein a same process step is used to form spacer of the two transistors.

4. The method of claim 1 wherein a same process step is used to form gate contacts of the two transistors.

5. The method of claim 1 further comprising:

forming two insulative members on the first and second bodies using a same process step;

shielding the second transistor to remove the first insulative member.

6. A method comprising:

forming at least two semiconductor bodies from a semiconductor layer;

forming an insulative member on the second semiconductor body;

patterning a dielectric layer to form two gate dielectric layers on the two semiconductor bodies; and

forming a conductive layer to form a first metal gate surrounding on three sides of the first semiconductor body and two independent metal gates on opposite sides of the second semiconductor body, the insulative member formed between the two independent metal gates, wherein the semiconductor bodies, the gate dielectric layers and the metal gates are formed in a same process step.

7. The method of claim 6, further comprising patterning a sacrificial layer to form sacrificial gates for the two semiconductor bodies.

8. The method of claim 6, further comprising planarizing the sacrificial layer before patterning.

9. The method of claim 6, further comprising forming a hardmask layer over the sacrificial layer after planarizing.

10. The method of claim 6, wherein planarizing is further characterized as using an etch-back process to planarize the surface of the sacrificial layer.

11. The method of claim 6, further comprising removing the sacrificial gates before forming the metal gates.

12. The method of claim 6, further comprising patterning a spacer layer to form spacers for the two semiconductor bodies.

13. The method of claim 6, wherein forming an insulative member on one semiconductor body comprises patterning an insulative layer to form two insulative members overlying the two semiconductor bodies;

removing an insulative member on the first semiconductor body.

14. The method of claim 13, further comprising enclosing sacrificial gates and the semiconductor bodies with the overlying insulative members in a dielectric layer.

15. The method of claim 14, further comprising planarizing the dielectric layer to expose portions of the insulative members before removing an insulative member.

16. An integrated circuit formed by a process that includes:

forming a first transistor on a substrate having a first body surrounded on three sides by a first metal gate; and

forming a second transistor on the substrate having a second body having two independent metal gates on opposite sides of the second body, and an insulative member formed on the second body, the insulative member is formed between the two independent metal gates,

wherein the first and second transistors are formed in a same process flow.

17. The integrated circuit of claim 16, wherein the semiconductor bodies comprise monocrystalline silicon.

18. The integrated circuit of claim 16, wherein the insulative member comprises silicon nitride.

19. The integrated circuit of claim 16, wherein the first and second gate dielectrics are made of a high dielectric constant material selected from the group consisting of metal oxides, PZT or BST.

20. The integrated circuit of claim 16, wherein the first, second and third gate electrodes are made of a material selected from the group consisting of tungsten, tantalum and titanium.