Printed TFT and TFT array with self-aligned gate
First Claim
Patent Images
1. A thin film transistor comprisinga gate contact formed from a state-switchable material;
- a gate dielectric layer formed over the gate contact;
a source-drain layer including a source contact, and a drain contact formed with a source-drain layer material, wherein any portion of the state-switchable material covered by the source contact and the drain contact is non-conductive and any portion of the state-switchable material not located under the source contact and the drain contact is conductive; and
a semiconductor material formed between the source contact and the drain contact.
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Accused Products
Abstract
A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain material. An area of the gate contact is exposed to a form of energy, wherein the energy transforms a portion of the state switchable material from a non-conductive material to a conductive material, the conductive portion defining the gate contact. A semiconductor material is formed between the source contact and the drain contact.
20 Citations
19 Claims
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1. A thin film transistor comprising
a gate contact formed from a state-switchable material; -
a gate dielectric layer formed over the gate contact; a source-drain layer including a source contact, and a drain contact formed with a source-drain layer material, wherein any portion of the state-switchable material covered by the source contact and the drain contact is non-conductive and any portion of the state-switchable material not located under the source contact and the drain contact is conductive; and a semiconductor material formed between the source contact and the drain contact. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 15)
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10. A self-aligning thin film transistor comprising:
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a gate contact area comprised of a state-switchable material a gate dielectric configured to isolate the gate contact area; a source-drain layer, including a source contact and a drain contact configured with a source-drain layer material; an exposed portion of the gate contact area which has been exposed to a form of energy, wherein the exposed portion of the gate contact area is conductive and the exposed portion of the gate contact area is a gate contact, wherein at least some of the state-switchable material is covered by the drain contact and the source contact, and the drain contact and the source contact are configured to block the energy from reaching the portion of the state-switchable material located under the drain contact and the source contact, and wherein at least a portion of the state-switchable material under the drain contact and the source contact is non-conductive; and a semi-conductor layer of a semiconductor material is positioned between the source contact and the drain contact. - View Dependent Claims (11, 12, 13, 14, 16)
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17. A self-aligning thin film transistor comprising:
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a gate contact area comprised of a state-switchable material; a gate dielectric which isolates the gate contact area; a source-drain layer, including a source contact and a drain contact with a source-drain layer material; an exposed portion of the gate contact area, wherein the exposed portion of the gate contact area is conductive and the exposed portion of the gate contact area is a gate contact; and a semi-conductor layer of a semiconductor material between the source contact and the drain contact, wherein the drain contact and the source contact are configured to block the source of energy from reaching the portion of the state-switchable material covered by the drain contact and the source contact, wherein the covered portion of the state-switchable material is non-conductive and the exposed portion of the state-switchable material is conductive. - View Dependent Claims (18, 19)
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Specification