Locating short circuits in printed circuit boards

• US 8,269,505 B2
• Filed: 12/15/2009
• Issued: 09/18/2012
• Est. Priority Date: 12/15/2009
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cases, Moises, Mutnury, Bhyrav M., Rodrigues, Terence
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): Brown, Lamarr
• Application Number:
  US12/638,044
• Publication Number:
  US 20110140709A1
• Time in Patent Office: 1,008 Days
• Field of Search: 324/528, 324/527, 324/532, 324/533, 324/534, 324/535, 324/754.01, 324/763.01, 324/763.02
• US Class Current: 324/528
• CPC Class Codes: G01R 31/2812 Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance of connections G01R31/66

Abstract

One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.

Claims

1. A method of locating a short circuit between two layers of a printed circuit board, the method comprising:

selecting first, second, and third non-collinear test points in one of the two layers;

injecting a first test signal at the first test point and determining a first distance to the short circuit according to a signal reflection from the injected first test signal;

injecting a second test signal at the second test point and determining a second distance to the short circuit according to a signal reflection from the injected second test signal;

injecting a third test signal at the third test point and determining a third distance to the short circuit according to the signal reflection from the injected third test signal; and

identifying the location of the short circuit as being the first distance from the first test point, the second distance from the second test point, and the third distance from the third test point.

2. The method of claim 1, further comprising:

determining the first distance according to a first time interval required for a signal reflection from the first test signal to reach the first test point;

determining the second distance according to a second time interval required for a signal reflection from the second test signal to reach the second test point; and

determining the third distance according to a third time interval required for a signal reflection from the third test signal to reach the third test point.

3. The method of claim 2, further comprising:

determining the first distance as one half of the first time interval multiplied by the propagation rate of the first test signal through the selected layer;

determining the second distance as one half of the second time interval multiplied by the propagation rate of the second test signal through the selected layer; and

determining the third distance as one half of the third time interval multiplied by the propagation rate of the third test signal through the selected layer.

4. The method of claim 2, further comprising:

identifying a voltage drop in each test signal as the respective signal reflection; and

determining the first, second, and third time intervals according to the timing of the voltage drops.

5. The method of claim 1, wherein the first layer is one of a ground layer and a power layer and the second layer is the other of a ground layer and a power layer.

6. The method of claim 1, further comprising:

generating each of the first, second, and third test signals as a step voltage signal.

7. The method of claim 1, further comprising:

selecting the test points at locations aligned with vias of the printed circuit board; and

injecting each test signal at the contact pad connected to the respective via.

8. A method of locating a short circuit between two layers of a printed circuit board, the method comprising:

selecting first and second test points in one of the two layers within 1 cm of an edge of the printed circuit board;

injecting a first test signal at the first test point and determining a first distance to the short circuit according to a signal reflection from the injected first test signal;

injecting a second test signal at the second test point and obtaining a second distance to the short circuit according to a signal reflection from the injected second test signal; and

identifying the location of the short circuit as a unique point located the first distance from the first test point, the second distance from the second test point, and within the printed circuit board.

9. The method of claim 8, further comprising identifying two locations located the first distance from the first test point and the second distance from the second test point and eliminating one of the identified locations that does not lie on the printed circuit board.

10. The method of claim 8, further comprising:

determining the first distance according to a first time interval required for a signal reflection from the first test signal to reach the first test point; and

determining the second distance according to a second time interval required for a signal reflection from the second test signal to reach the second test point.

11. The method of claim 10, further comprising:

determining the first distance as the first time interval multiplied by the propagation rate of the first test signal through the selected layer; and

determining the second distance as the second time interval multiplied by the propagation rate of the second test signal through the selected layer.

12. The method of claim 10, further comprising:

identifying a voltage drop in each test signal as the respective signal reflection; and

determining the first, second, and third time intervals according to the timing of the voltage drops.

13. The method of claim 9, wherein the first layer is one of a ground layer and a power layer and the second layer is the other of a ground layer and a power layer.

14. The method of claim 9, further comprising:

generating each of the first, second, and third test signals as a step voltage signal.

15. The method of claim 9, further comprising:

selecting the test points at locations aligned with vias of the printed circuit board; and

injecting each test signal at the contact pad connected to the respective via.

16. A computer program product including computer usable program code embodied on a non-transitory computer usable storage medium for locating a short circuit in a printed circuit board, the computer program product including:

computer usable program code for injecting a first test signal at a first test point and determining a first distance to the short circuit according to a signal reflection from the injected first test signal;

computer usable program code for injecting a second test signal at a second test point and obtaining a second distance to the short circuit according to a signal reflection from the injected second test signal;

computer usable program code for injecting a third test signal at a third test point and obtaining a third distance to the short circuit according to the signal reflection from the injected third test signal; and

computer usable program code for identifying the location of the short circuit as being the first distance from the first test point, the second distance from the second test point, and the third distance from the third test point.