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Timing skew error correction apparatus and methods

  • US 8,269,528 B2
  • Filed: 11/18/2010
  • Issued: 09/18/2012
  • Est. Priority Date: 11/18/2010
  • Status: Active Grant
First Claim
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1. An analog signal sampling circuit, comprising:

  • a first signal capture module to sample a first phase of an analog signal by capturing a magnitude of the first phase upon receipt of a clock transition from a first capture clock;

    a first clock delay module coupled to the first signal capture module to delay a common clock by a first delay period to generate the first capture clock;

    a second signal capture module to sample a second phase of the analog signal by capturing a magnitude of the second phase upon receipt of a clock transition from a second capture clock; and

    a second clock delay module coupled to the common clock and to the second signal capture module to delay the common clock by a second delay period to generate the second capture clock.

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