Timing skew error correction apparatus and methods

• US 8,269,528 B2
• Filed: 11/18/2010
• Issued: 09/18/2012
• Est. Priority Date: 11/18/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Payne, Robert Floyd, Pratt, Philip M., Smith, William David
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Hernandez, William
• Application Number:
  US12/948,757
• Publication Number:
  US 20120126869A1
• Time in Patent Office: 670 Days
• Field of Search: 327 91- 96, 341122-125
• US Class Current: 327/94
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03M 1/0624 by synchronisation
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods

Abstract

Apparatus and methods disclosed herein operate to compensate for skew between inverse phases (e.g., differential phases) of an analog signal appearing at the inputs of an analog signal capture circuit such as a track-and-hold or sample-and-hold circuit associated with an ADC or similar device. Each of two capture clocks is used to capture one of the inverse phases. One or more delay circuits are configured to create a differential delay between clock transitions associated with the two capture clocks. The differential delay is proportional to the input skew between the inverse phases. The phases are consequently sampled at substantially identical points on a phase domain axis. Embodiments operate to create phase sampling synchronicity and to thereby decrease the amplitude of a common-mode signal component that results from the skew. Increased linearity and decreased distortion may result.

Claims

1. An analog signal sampling circuit, comprising:

a first signal capture module to sample a first phase of an analog signal by capturing a magnitude of the first phase upon receipt of a clock transition from a first capture clock;

a first clock delay module coupled to the first signal capture module to delay a common clock by a first delay period to generate the first capture clock;

a second signal capture module to sample a second phase of the analog signal by capturing a magnitude of the second phase upon receipt of a clock transition from a second capture clock; and

a second clock delay module coupled to the common clock and to the second signal capture module to delay the common clock by a second delay period to generate the second capture clock.

2. The sampling circuit of claim 1, the first clock delay module and the second clock delay module configured to establish at least one of the first delay period or the second delay period such that the first phase and second phase are sampled at substantially identical points on a phase axis associated with the analog signal.

3. The sampling circuit of claim 1, at least one of the first signal capture module or the second signal capture module comprising at least one of a track-and-hold circuit or a sample-and-hold circuit.

4. The sampling circuit of claim 1, at least one of the first clock delay module or the second clock delay module further comprising:

at least one delay element; and

at least one delay control element coupled to the delay element to establish at least one of the first delay period or the second delay period.

5. The sampling circuit of claim 4, the delay element comprising an inverter.

6. The sampling circuit of claim 4, further comprising:

a differential phase detector coupled to the first signal capture module and to the second signal capture module to determine a phase difference between the first phase and the second phase; and

a delay control module coupled to the differential phase detector to act upon the delay control element to adjust at least one of the first delay period or the second delay period in an amount proportional to the phase difference such that the first phase and second phase are sampled at substantially identical points on a phase axis associated with the analog signal.

7. The sampling circuit of claim 1, at least one of the first clock delay module or the second clock delay module further comprising:

at least one supply voltage dependent delay element; and

a power supply coupled to the supply voltage dependent delay element to set a voltage level to control an amount of propagation delay associated with the supply voltage dependent delay element and to establish a position on a time axis of at least one of the first capture clock or the second capture clock such that the first phase and the second phase are sampled at substantially identical points on a phase axis associated with the analog signal.

8. The sampling circuit of claim 7, the power supply comprising a voltage-variable power supply.

9. The sampling circuit of claim 1, at least one of the first clock delay module or the second clock delay module further comprising:

at least one load capacitance dependent delay element; and

a tuned load capacitor coupled to the output of the load capacitance dependent delay element to set an amount of propagation delay associated with the load capacitance dependent delay element and to establish a position on a time axis of at least one of the first capture clock or the second capture clock such that the first phase and second phase are sampled at substantially identical points on a phase axis associated with the analog signal.

10. The sampling circuit of claim 9, the tuned load capacitor comprising a variable capacitor.

11. The sampling circuit of claim 1, at least one of the first clock delay module or the second clock delay module further comprising:

at least one current-starved delay element; and

a tuned current source coupled to the current-starved delay element to provide a control current to control an amount of propagation delay associated with the current-starved delay element and to establish a position on a time axis of at least one of the first capture clock or the second capture clock such that the first phase and second phase are sampled at substantially identical points on a phase axis associated with the analog signal.

12. The sampling circuit of claim 11, the tuned current source comprising a variable current source.

13. A method of analog signal capture, comprising:

delaying a common clock by a first delay period to produce a first capture clock;

sampling a first phase of an analog signal by capturing a magnitude of the first phase upon receipt of a clock transition from the first capture clock;

delaying the common clock by a second delay period to produce a second capture clock; and

sampling a second phase of the analog signal by capturing a magnitude of the second phase upon receipt of a clock transition from the second capture clock.

14. The method of claim 13, further comprising:

establishing at least one of the first delay period or the second delay period such that the first and second capture clocks sample the first phase and the second phase at substantially identical points on a phase axis associated with the analog signal.

15. The method of claim 13, further comprising:

selecting a power supply voltage associated with a clock delay element;

adjusting at least one of the first delay period or the second delay period in proportion to the power supply voltage such that the first phase and the second phase are sampled at substantially identical points on a phase axis associated with the analog signal.

16. The method of claim 13, further comprising:

selecting a load capacitance associated with an output of a clock delay element;

adjusting at least one of the first delay period or the second delay period in proportion to the load capacitance such that the first phase and the second phase are sampled at substantially identical points on a phase axis associated with the analog signal using the first delay period and/or the second delay period.

17. The method of claim 13, further comprising:

selecting a magnitude of an electrical current supplied by a current source associated with a current-starved clock delay element;

adjusting at least one of the first delay period or the second delay period in proportion to the magnitude of the electrical current such that the first phase and the second phase are sampled at substantially identical points on a phase axis associated with the analog signal using the first delay period and/or the second delay period.

18. The method of claim 13, further comprising:

determining a phase difference between the first phase and the second phase;

determining a differential clock delay period proportional to the phase difference;

adjusting at least one of the first delay period or the second delay period in proportion to the differential clock delay period such that the first phase and the second phase are sampled at substantially identical points on a phase axis associated with the analog signal.

19. An analog signal sampling circuit, comprising:

a first track-and-hold circuit to capture a magnitude of a first phase of an analog signal upon receipt of a clock transition from a first capture clock;

at least one first inverter coupled to the first track-and-hold circuit to provide a first propagation delay to a common clock to produce the first capture clock;

a first power supply coupled to the first inverter to provide a first supply voltage to the first inverter to adjust a period of the first propagation delay in proportion to the first supply voltage;

a second track-and-hold circuit to capture a magnitude of a second phase of the analog signal upon receipt of a clock transition from a second capture clock;

at least one second inverter coupled to the second track-and-hold circuit to provide a second propagation delay to the common clock to produce the second capture clock;

a second power supply coupled to the second inverter to provide a second supply voltage to the second inverter to adjust a period of the second propagation delay in proportion to the second supply voltage;

a differential phase detector coupled to the first track-and-hold circuit and to the second track-and-hold circuit, the differential phase detector to determine a phase difference between the first phase and the second phase; and

a delay control module coupled to the differential phase detector to act upon the first and second power supplies to adjust the first and second supply voltages to the first and second inverters in proportion to the phase difference such that the first phase and the second phase are sampled at substantially identical points on a phase axis associated with the analog signal.