Programmable power supervisor

• US 8,269,531 B1
• Filed: 07/13/2011
• Issued: 09/18/2012
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Wright, David G.
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Hernandez, William
• Application Number:
  US13/182,264
• Time in Patent Office: 433 Days
• Field of Search: 327/142, 327/143, 327/198
• US Class Current: 327/143
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H03L 5/02 of power
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system can include at least one power supervisor coupled between two supply voltage terminals and including a comparator circuit configured to assert at least one output signal in response to a voltage between the terminals varying from at least one trip voltage, and a memory coupled to a programming interface for storing values that establish the at least one trip voltage; and circuitry coupled between the terminals that receives the at least one output signal, and configured to hold at least a portion of the circuitry in one mode of operation in response to the assertion of at least one output signal.

Claims

1. A system, comprising:

at least one power supervisor coupled between two supply voltage terminals and including

a comparator circuit configured to assert at least one output signal in response to a voltage between the terminals varying from at least one trip voltage, and

a memory coupled to a programming interface for storing values that establish the at least one trip voltage; and

circuitry coupled between the terminals that receives the at least one output signal, and configured to hold at least a portion of the circuitry in one mode of operation in response to the assertion of at the least one output signal.

2. The system of claim 1, wherein:

the at least one power supervisor is formed in a first integrated circuit (IC); and

the circuitry is formed in a second IC different from the first IC.

3. The system of claim 1, wherein:

the at least one power supervisor is combined with power circuitry.

4. The system of claim 1, wherein:

the programming interface comprises a serial communication interface.

5. The system of claim 4, wherein:

the serial communication interface is configured to receive values from at least one of the terminals.

6. The system of claim 1, wherein:

the at least one output signal includes an interrupt signal; and

the comparator circuit asserts the interrupt signal in response to the voltage between the terminals varying from a first trip voltage;

wherein

the first trip voltage is established by values stored in the memory.

7. The system of claim 6, wherein:

the at least one output signal further includes a reset signal; and

the comparator circuit asserts the reset signal in response to the voltage between the terminals varying from a second trip voltage;

wherein

the second trip voltage is established by values stored in the memory.

8. The system of claim 1, wherein:

the memory comprises a non-volatile memory.

9. A method, comprising:

writing threshold values to a memory;

asserting at least one output signal in response to a power supply voltage varying from at least one trip voltage established by the threshold values; and

holding at least a portion of circuitry in one mode of operation in response to the at least one output signal being asserted;

wherein

the circuitry is coupled to receive power from power supply terminals.

10. The method of claim 9, wherein:

writing threshold values includes writing to the memory through a serial interface.

11. The method of claim 10, wherein:

writing through the serial interface includes writing through at least one of the power supply terminals.

12. The method of claim 9, wherein:

writing threshold values includes programming a non-volatile memory.

13. The method of claim 9, wherein:

asserting the at least one output signal includes asserting an interrupt signal.

14. The method of claim 13, wherein:

asserting the at least one output signal further includes asserting a reset signal.

15. A method, comprising:

storing programmable values in a memory;

receiving a power supply voltage; and

asserting at least one output signal based on the power supply voltage and at least one condition that varies according to the programmable values;

wherein

the at least one condition includes at least one of

a threshold voltage that varies according to the programmable values and asserting the at least one output signal includes asserting one output signal in response to the power supply voltage falling below the threshold voltage, and

a delay that varies according to the programmable values and asserting at the least one output signal includes asserting one output signal in response to the power supply voltage falling below a threshold voltage for longer than the delay.

16. The method of claim 15, further including:

receiving the at least one output signal at circuitry coupled to the power supply voltage; and

holding at least a portion of the circuitry in one mode of operation in response to at least the one output signal being asserted.

17. The method of claim 16, wherein:

asserting at least one output signal includes outputting a signal from a supervisor module;

wherein

the supervisor and circuitry are combined circuit elements.

18. The method of claim 16, wherein:

asserting at least one output signal includes outputting a signal from a supervisor module;

wherein

the supervisor and circuitry are separate circuit elements.