Pipelined ADC having a three-level DAC elements

• US 8,269,661 B2
• Filed: 10/14/2010
• Issued: 09/18/2012
• Est. Priority Date: 10/14/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Corsi, Marco, Payne, Robert F.
• Primary Examiner(s): Nguyen, Khai M
• Application Number:
  US12/904,688
• Publication Number:
  US 20120092199A1
• Time in Patent Office: 705 Days
• Field of Search: 341/161, 341/162
• US Class Current: 341/162
• CPC Class Codes: H03M 1/069 by range overlap between successive stages or steps
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches'"'"' current sources and reduces the amount of area used.

Claims

1. An apparatus comprising:

a logic circuit that includes;

a decoder that receives a control word and that generates a plurality of control signals from the control word; and

a plurality of predrivers that are each coupled to the decoder so as to receive at least one of the control signals; and

a plurality of three-state digital-to-analog converter (DAC) switches, wherein each three-state DAC is coupled to at least one of the predrivers, wherein each of the plurality of three-state DAC switches includes;

a current source;

a first transistor that is coupled to the current source and an associated predriver, wherein the associated predriver controls the first transistor;

a second transistor that is coupled to the current source and the associated predriver, wherein the associated predriver controls the second transistor; and

a third transistor that is coupled between the current source and ground and that is coupled to the associated predriver, wherein the associated predriver controls the third transistor.

2. The apparatus of claim 1, wherein the first second and third transistors are NPN transistors, and wherein each of the first, second, and third transistors is coupled to the current source at emitter and to the associated predriver at its base.

3. An apparatus comprising:

a logic circuit that includes;

a decoder that receives a control word and that generates a plurality of control signals from the control word; and

a plurality of predrivers that are each coupled to the decoder so as to receive at least one of the control signals, wherein each predriver includes;

a first current source;

a second current source;

a first cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder; and

a second cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder; and

a plurality of three-state DAC switches, wherein each three-state DAC is coupled to at least one of the predrivers.

4. The apparatus of claim 3, wherein the first cascaded set further comprises:

a first bipolar transistor that is coupled to the decoder at its base and to an associated three-state DAC switch at its collector;

a second bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector;

a third bipolar transistor that is coupled to the decoder at its base, to the emitters of the first and second bipolar transistors at its collector, and to the first current source at its emitter; and

a fourth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the first current source at its emitter.

5. The apparatus of claim 4, wherein the second cascaded set further comprises:

a fifth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector;

a sixth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector;

a seventh bipolar transistor that is coupled to the decoder at its base, to the emitters of the fifth and sixth bipolar transistors at its collector, and to the second current source at its emitter; and

an eighth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the second current source at its emitter.

6. An apparatus comprising:

a digital output circuit; and

a pipeline having a plurality of analog-to-digital converter (ADC) stages that are coupled in together in a sequence, wherein each ADC stage includes;

a track-and-hold (T/H) circuit;

a sub-ADC that is coupled to the T/H circuit and to the digital output circuit;

a DAC that is coupled to the sub-ADC, wherein the DAC includes;

a decoder that is coupled to the sub-ADC;

a plurality of predrivers that are each coupled to the decoder; and

a plurality of three-state DAC switches, wherein each three-state DAC is coupled to at least one of the predrivers, wherein each of the plurality of three-state DAC switches includes;

a current source;

a first transistor that is coupled to the current source and an associated predriver, wherein the associated predriver controls the first transistor;

a second transistor that is coupled to the current source and the associated predriver, wherein the associated predriver controls the second transistor; and

a third transistor that is coupled between the current source and ground and that is coupled to the associated predriver, wherein the associated predriver controls the third transistor; and

a residue amplifier that is coupled to the DAC and the T/H circuit.

7. The apparatus of claim 6, wherein the first second and third transistors are NPN transistors, and wherein each of the first, second, and third transistors is coupled to the current source at emitter and to the associated predriver at its base.

8. An apparatus comprising:

a digital output circuit; and

a pipeline having a plurality of analog-to-digital converter (ADC) stages that are coupled in together in a sequence, wherein each ADC stage includes;

a track-and-hold (T/H) circuit;

a sub-ADC that is coupled to the T/H circuit and to the digital output circuit;

a DAC that is coupled to the sub-ADC, wherein the DAC includes;

a decoder that is coupled to the sub-ADC;

a plurality of predrivers that are each coupled to the decoder, wherein each predriver includes;

a first current source;

a second current source;

a first cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder; and

a second cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder;

a plurality of three-state DAC switches, wherein each three-state DAC is coupled to at least one of the predrivers; and

a residue amplifier that is coupled to the DAC and the T/H circuit.

9. The apparatus of claim 8, wherein the first cascaded set further comprises:

a first bipolar transistor that is coupled to the decoder at its base and to an associated three-state DAC switch at its collector;

a second bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector;

a third bipolar transistor that is coupled to the decoder at its base, to the emitters of the first and second bipolar transistors at its collector, and to the first current source at its emitter; and

a fourth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the first current source at its emitter.

10. The apparatus of claim 9, wherein the second cascaded set further comprises:

a fifth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector;

a sixth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector;

a seventh bipolar transistor that is coupled to the decoder at its base, to the emitters of the fifth and sixth bipolar transistors at its collector, and to the second current source at its emitter; and

an eighth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the second current source at its emitter.

11. The apparatus of claim 10, wherein the pipeline further comprises:

a buffer that receives an analog input signal and that is coupled to the first ADC stage of the sequence; and

a plurality of output ADCs that are each coupled to the last ADC stage of the sequence and to the digital output circuit.

12. An apparatus comprising:

a digital output circuit that generates a digital output signal;

a buffer that receives an analog input signal;

a plurality of ADC stages that are coupled in together in a sequence, the first ADC stage of the sequence is coupled to the buffer, and wherein each ADC stage includes;

a T/H circuit;

a sub-ADC that is coupled to the T/H circuit and to the digital output circuit;

a DAC that is coupled to the sub-ADC, wherein the DAC includes;

a decoder that is coupled to the sub-ADC;

a plurality of predrivers, wherein each predriver includes;

a first current source;

a second current source;

a first cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder;

a second cascaded set of differential pairs of transistors that is coupled to first current source and to the decoder; and

a plurality of three-state DAC switches, wherein each three-state DAC includes;

a current source;

a first transistor that is coupled to the current source and an associated predriver, wherein the associated predriver controls the first transistor;

a second transistor that is coupled to the current source and the associated predriver, wherein the associated predriver controls the second transistor; and

a third transistor that is coupled between the current source and ground and that is coupled to the associated predriver, wherein the associated predriver controls the third transistor; and

a residue amplifier that is coupled to the first and second transistors from each three-state DAC switch and the T/H circuit; and

an output ADC that is coupled to the last ADC stage of the sequence and the digital output circuit.

13. The apparatus of claim 12, wherein the first second and third transistors are bipolar transistors, and wherein each of the first, second, and third transistors is coupled to the current source at emitter and to the associated predriver at its base.

14. The apparatus of claim 12, wherein the first cascaded set further comprises:

a first bipolar transistor that is coupled to the decoder at its base and to an associated three-state DAC switch at its collector;

a second bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector;

a third bipolar transistor that is coupled to the decoder at its base, to the emitters of the first and second bipolar transistors at its collector, and to the first current source at its emitter; and

a fourth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the first current source at its emitter.

15. The apparatus of claim 14, wherein the second cascaded set further comprises:

a fifth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector;

a sixth bipolar transistor that is coupled to the decoder at its base and to the associated three-state DAC switch at its collector;

a seventh bipolar transistor that is coupled to the decoder at its base, to the emitters of the fifth and sixth bipolar transistors at its collector, and to the second current source at its emitter; and

an eighth bipolar transistor that is coupled to the decoder at its base, to the associated three-state DAC switch at its collector, and to the second current source at its emitter.