Electrostatic discharge protection element and electrostatic discharge protection chip and method of producing the same

• US 8,270,131 B2
• Filed: 07/31/2009
• Issued: 09/18/2012
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Klein, Wolfgang, Taddiken, Hans, Bakalski, Winfried
• Primary Examiner(s): SALCE, PATRICK R
• Application Number:
  US12/533,919
• Publication Number:
  US 20110026174A1
• Time in Patent Office: 1,145 Days
• Field of Search: 361/56, 361/91.1, 361/111, 257/355, 257/656, 257/450, 257544-550, 257/927, 257/929, 257/E31.061
• US Class Current: 361/56
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/8618 Diodes with bulk potential barrier, e.g. Camel diodes, Planar Doped Barrier diodes, Graded bandgap diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An electrostatic discharge (ESD) protection element is described, the ESD protection element including a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.

Claims

1. An electrostatic discharge (ESD) protection element comprising:

a collector area having a first conductivity type;

a first barrier area bordering on the collector area, the first barrier area having a second conductivity type;

a semiconductor area bordering on the first barrier area, the semiconductor area being an intrinsic semiconductor area, or a semiconductor area having the first or second conductivity type and a dopant concentration that is lower than a dopant concentration of the first barrier area;

a second barrier area bordering on the semiconductor area, the second barrier area having the second conductivity type and a higher dopant concentration than the semiconductor area; and

an emitter area bordering on the second barrier area, the emitter area having the first conductivity type;

a third barrier area bordering on the semiconductor area, the third barrier area having the first conductivity type and a higher dopant concentration than the semiconductor area; and

a base area bordering on the third barrier area, the base area having the second conductivity type,

wherein the dopant concentration of the third barrier area is such that the third barrier area is more than 95% or fully depleted of charge carriers of the first conductivity type when no voltage is applied to the electrostatic discharge protection element,

wherein the dopant concentrations of the first barrier area and of the second barrier area are such that the first barrier area and the second barrier area are more than 95% depleted of charge carriers of the second conductivity type when no voltage is applied to the electrostatic discharge protection element; and

wherein the base area is connected to the emitter area via an electrical connection line.

2. The electrostatic discharge protection element according to claim 1, wherein the dopant concentration of the first barrier area and the dopant concentration of the second barrier area are such that the first barrier area and the second barrier area are fully depleted of charge carriers of the second conductivity type when no voltage is applied to the electrostatic discharge protection element.

3. The electrostatic discharge protection element according to claim 1, wherein the collector area, the first barrier area, the semiconductor area, the second barrier area and the emitter area comprise a semiconductor material that has a higher bandgap than silicon.

4. The electrostatic discharge protection element according to claim 3, wherein the collector area, the first barrier area, the semiconductor area, the second barrier area and the emitter area comprise silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN) or diamond as the semiconductor material.

5. The electrostatic discharge protection element according to claim 1, wherein a material with the first conductivity type is an n-doped semiconductor material and a material with the second conductivity is a p-doped semiconductor material.

6. The electrostatic discharge protection element according to claim 1, wherein the electrostatic discharge protection element is a passive electrostatic discharge protection element having only two contacts as external contacts, a data line contact connected to the collector area to connect the collector area with a data line that is to be protected from the electrostatic discharge, and a second contact connected to the emitter area to connect the emitter area with a ground contact.

7. An electrostatic discharge (ESD) protection element comprising:

a collector area having a first conductivity type;

a first barrier area bordering on the collector area, the first barrier area having a second conductivity type;

a semiconductor area bordering on the first barrier area, the semiconductor area being an intrinsic semiconductor area, or a semiconductor area having the first or second conductivity type and a dopant concentration that is lower than a dopant concentration of the first barrier area;

a second barrier area bordering on the semiconductor area, the second barrier area having the second conductivity type and a higher dopant concentration than the semiconductor area; and

an emitter area bordering on the second barrier area, the emitter area having the first conductivity type;

wherein the dopant concentrations of the first barrier area and of the second barrier area are such that the first barrier area and the second barrier area are more than 95% depleted of charge carriers of the second conductivity type when no voltage is applied to the electrostatic discharge protection element;

wherein the semiconductor area is an epitaxy layer bordering on a substrate layer, the substrate layer having the first or second conductivity type and a dopant concentration that is higher than the dopant concentration of the epitaxy layer;

wherein the electrostatic discharge protection element further comprises a barrier layer arranged between the epitaxy layer and the substrate layer, the barrier layer having the first conductivity type and a higher dopant concentration than the semiconductor area; and

wherein the dopant concentration of the barrier layer is such that the barrier layer is depleted more than 95% or fully depleted when no voltage is applied to the electrostatic discharge protection element.

8. A passive chip comprising:

a ground contact to connect the chip with an external ground voltage;

a data line contact to connect the chip with an external data line; and

an electrostatic discharge (ESD) protection element, the electrostatic discharge protection element comprising

a collector area having a first conductivity type;

a first barrier area bordering on the collector area, the first barrier area having a second conductivity type;

a semiconductor area bordering on the first barrier area, the semiconductor area being an intrinsic semiconductor area, or having the first or second conductivity type and a dopant concentration that is lower than a dopant concentration of the first barrier area;

a second barrier area bordering on the semiconductor area, the second barrier area having the second conductivity type and a higher dopant concentration than the semiconductor area; and

an emitter area bordering on the second barrier area, the emitter area having the first conductivity type,

wherein the dopant concentration of the first barrier area and of the second barrier area are such that the first barrier area and the second barrier area are more than 95% depleted or fully depleted of charge carriers of the second conductivity type, when no voltage is applied to the electrostatic discharge protection element; and

wherein the ground contact is connected to the emitter area and the data line contact is connected to the collector area.

9. The passive chip according to claim 8, the passive chip being an electrostatic discharge protection chip, which has only the ground contact and the data line contact as external contacts.

10. The passive chip according to claim 8, comprising:

a plurality of data line contacts to connect the chip with a plurality of external data lines; and

a plurality of electrostatic discharge (ESD) protection elements, each of the electrostatic discharge protection elements comprising;

a collector area having a first conductivity type;

a first barrier area bordering on the collector area, the first barrier area having a second conductivity type;

a semiconductor area bordering on the first barrier area, the semiconductor area being an intrinsic semiconductor area, or having the first or second conductivity type and a dopant concentration that is lower than a dopant concentration of the first barrier area;

a second barrier area bordering on the semiconductor area, the second barrier area having the second conductivity type and a higher dopant concentration than the semiconductor area; and

an emitter area bordering on the second barrier area, the emitter area having the first conductivity type,

wherein the dopant concentration of the first barrier area and of the second barrier area are such that the first barrier area and the second barrier area are more than 95% depleted or fully depleted of charge carriers of the second conductivity type, when no voltage is applied to the electrostatic discharge protection element;

wherein the first and second conductivity types can differ between different electrostatic discharge protection elements of the plurality of discharge protection elements; and

wherein the ground contact is connected to the plurality of emitter areas, and each data line contact of the plurality of data line contacts is connected to a different collector area of the plurality of collector areas.

11. The passive chip according to claim 10, the passive chip being a passive electrostatic discharge protection chip, which has only the ground contact and the plurality of data line contacts as external contacts.

12. An electrostatic discharge protection element comprising a diode structure, the diode structure comprising:

a cathode area having a first conductivity type;

a first barrier area bordering on the cathode area, the first barrier area having a second conductivity type, that differs from the first conductivity type;

a semiconductor area bordering on the first barrier area, the semiconductor area being an intrinsic semiconductor area, or having the first or second conductivity type and a dopant concentration that is lower than a dopant concentration of the first barrier area;

a second barrier area bordering on the semiconductor area, the second barrier area having the first conductivity type and a higher dopant concentration than the semiconductor area; and

an anode area bordering on the second barrier area, the anode area having the second conductivity type,

wherein the dopant concentration of the first barrier area and the dopant concentration of the second barrier area are such that the first barrier area and the second barrier are more than 95% or fully depleted when no bias voltage is applied to the diode structure;

wherein the electrostatic discharge protection element comprises a further diode structure, the further diode structure comprising;

a further cathode area having the first conductivity type;

a further first barrier area bordering on the further cathode area, the further first barrier area having the second conductivity type;

a further semiconductor area bordering on the further first barrier area, the further semiconductor area being an intrinsic semiconductor area, or having the first or second conductivity type and a dopant concentration that is lower than a dopant concentration of the further first barrier area;

a further second barrier area bordering on the further semiconductor area, the further second barrier area having the first conductivity type and a higher dopant concentration than the further semiconductor area; and

a further anode area bordering on the further second barrier area, the further anode area having the second conductivity type,

wherein both the cathode area and the further anode area are connected to a data line contact of the electrostatic discharge protection element and wherein both the anode area and the further cathode area are connected to a ground contact of the electrostatic discharge protection element.

13. The electrostatic discharge protection element according to claim 12, wherein a forward breakdown voltage of the diode structure and a forward breakdown voltage of the further diode structure are smaller than reverse breakdown voltages of the diode structure and the further diode structure.

14. A method of producing an electrostatic discharge (ESD) protection element on a passive chip, the method comprising:

forming in a semiconductor substrate a collector area having a first conductivity type;

forming in the semiconductor substrate a first barrier area bordering on the collector area, the first barrier area having a second conductivity type;

forming in the semiconductor substrate a semiconductor area bordering on the first barrier area, the semiconductor area being an intrinsic semiconductor area, or a semiconductor area having the first or second conductivity type and a dopant concentration that is lower than a dopant concentration of the first barrier area;

forming in the semiconductor substrate a second barrier area bordering on the semiconductor area, the second barrier area having the second conductivity type and a higher dopant concentration than the semiconductor area; and

forming in the semiconductor substrate an emitter area bordering on the second barrier area, the emitter area having the first conductivity type;

forming a ground contact at the semiconductor substrate for connecting the chip with an external ground voltage, wherein the ground contact is electrically connected with the emitter area; and

forming a data line contact at the semiconductor substrate for connecting the chip with an external data line, wherein the data line contact is electrically connected with the collector area;

wherein the dopant concentration of the first barrier area and of the second barrier area are such that the first barrier area and the second barrier area are more than 95% or fully depleted of charge carriers of the second conductivity type, when no voltage is applied to the electrostatic discharge protection element.

15. The method according to claim 14, further comprising:

forming in the semiconductor substrate a third barrier area bordering on the semiconductor area, the third barrier area having the first conductivity type and a higher dopant concentration than the semiconductor area; and

forming in the semiconductor substrate a base area bordering on the third barrier area, the base area having the second conductivity type,

wherein the dopant concentration of the third barrier area is such that the third barrier area is more than 95% or fully depleted of charge carriers of the first conductivity type, when no voltage is applied to the electrostatic discharge protection element.

16. An electrostatic discharge (ESD) protection element comprising:

a collector area having a first conductivity type;

an emitter area having the first conductivity type;

a barrier area having a second conductivity type; and

a semiconductor area being an intrinsic semiconductor area, or a semiconductor area having the first or second conductivity type and a dopant concentration that is lower than a dopant concentration of the barrier area,

wherein the dopant concentrations of the barrier area and the semiconductor area are such that the barrier area is about 20-80% depleted of charge carriers of the second conductivity type when no voltage is applied to the electrostatic discharge protection element, and

wherein the barrier area borders on the emitter area, and the semiconductor area borders on the collector area and the barrier area, or

wherein the barrier area borders on the collector area, and the semiconductor area borders on the emitter area and the barrier area.