Exposed interconnect for a package on package system

• US 8,270,176 B2
• Filed: 08/08/2008
• Issued: 09/18/2012
• Est. Priority Date: 08/08/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Pagaila, Reza Argenty, Do, Byung Tai, Chua, Linda Pei Ee
• Primary Examiner(s): NGUYEN, HOA CAO
• Application Number:
  US12/188,995
• Publication Number:
  US 20100033941A1
• Time in Patent Office: 1,502 Days
• Field of Search: 361/760, 361/761, 361/764, 361/777, 361/782, 361/790, 361/792, 361/795, 361/807, 361809-810, 361/728, 361/729, 361735-737, 361/748, 174/250, 174/255, 174/259, 174/260, 174/261
• US Class Current: 361/760
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/31 : Structure, shape, material or disposition of the layer connectors after the connecting process
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An integrated circuit package system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation.

Claims

1. An integrated circuit package system comprising:

a substrate;

an integrated circuit mounted above the substrate;

an interposer connected to the integrated circuit with a wire-in-film adhesive;

an exposed interconnect connected to the substrate; and

an encapsulation encapsulating the integrated circuit and a portion of the exposed interconnect, the exposed interconnect exposed from the encapsulation; and

a passive component mounted to the exposed interconnect.

2. The system as claimed in claim 1 further comprising:

an upper surface of the exposed interconnect exposed from the encapsulation.

3. The system as claimed in claim 1 further comprising:

a bare side on the exposed interconnect exposed from the encapsulation.

4. The system as claimed in claim 1 further comprising:

a bare top on the upper surface of the exposed interconnect exposed from the encapsulation.

5. The system as claimed in claim 1 further comprising:

a package mounted above the interposer.

6. The system as claimed in claim 5 wherein:

the exposed interconnect has a stacked structure.

7. The system as claimed in claim 5 wherein:

the package is electrically connected to the interposer or to the exposed interconnect.

8. The system as claimed in claim 5 wherein:

the package is mounted on the encapsulation and over the interposer.

9. The system as claimed in claim 5 further comprising:

an inner package mounted to the interposer.

11. The method as claimed in claim 1 wherein:

encapsulating includes encapsulating the exposed interconnect having the upper surface of the exposed interconnect exposed.

12. The method as claimed in claim 1 wherein:

encapsulating includes encapsulating the exposed interconnect having the upper surface of the exposed interconnect exposed; and

further comprising;

forming a bare side on the exposed interconnect.

13. The method as claimed in claim 1 wherein:

encapsulating includes encapsulating the exposed interconnect; and

further comprising;

forming a bare top on the upper surface of the exposed interconnect.

10. A method for manufacturing an integrated circuit package system comprising:

providing a substrate;

mounting an integrated circuit above the substrate;

connecting an interposer to the integrated circuit with a wire-in-film adhesive;

connecting an exposed interconnect having an upper surface to the substrate;

encapsulating the integrated circuit and a portion of the exposed interconnect with an encapsulation, the exposed interconnect exposed from the encapsulation; and

mounting a passive component to the exposed interconnect.

14. A method for manufacturing an integrated circuit package system comprising:

providing a substrate;

mounting an integrated circuit above the substrate;

connecting an interposer to the integrated circuit with a wire-in-film adhesive;

connecting an exposed interconnect having an upper surface to the substrate;

encapsulating the integrated circuit and a portion of the exposed interconnect with an encapsulation having a mold riser above the interposer, the exposed interconnect exposed from the encapsulation; and

mounting a passive component to the exposed interconnect.

15. The method as claimed in claim 14 wherein:

connecting the exposed interconnect includes forming the exposed interconnect having a stacked structure.

16. The method as claimed in claim 14 further comprising:

connecting a second package electrically to the interposer or to the exposed interconnect.

17. The method as claimed in claim 14 further comprising:

mounting a package on the encapsulation and over the interposer.

18. The method as claimed in claim 14 further comprising:

connecting an inner package to the interposer.