Distributed flash memory storage manager systems

• US 8,270,194 B2
• Filed: 04/05/2010
• Issued: 09/18/2012
• Est. Priority Date: 04/07/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Zhou, Wei, Chu, Chee Hoe, Chang, Po-Chien
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Huerta, Pablo
• Application Number:
  US12/754,376
• Publication Number:
  US 20100254173A1
• Time in Patent Office: 897 Days
• Field of Search: 365/63
• US Class Current: 365/63
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0692 Multiconfiguration, e.g. local and global addressing
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or read data from the flash memory associated with various ones of the modules by routing the data through the flash memory storage circuitry of the modules. The system may also be able to relocate data for various reasons using such read and write operations. The flash memory storage circuitry of the modules keeps track of where data actually is in the flash memory.

Claims

1. A plurality of memory circuits, each of which is connected to a respective one of a plurality of integrated circuits (“

ICs”

), each of the ICs being connected to at least one of the other ICs by inter-IC connections so that an IC exchanges memory circuit data with another IC via the inter-IC connections, each of the ICs including memory manager circuitry comprising;

a logic block manager for maintaining a unique global identification (“

ID”

) for each block of data contained in any portion of any of the memory circuits, the global ID including a node ID identifying the IC that is connected to the memory circuit containing that block and a logical block number for that block;

a translator for maintaining a mapping between (1) the logical block number of each block contained in the memory circuit connected to the IC that includes that translator, and (2) a physical portion ID of a portion of that memory circuit that contains that block; and

a driver for receiving the physical portion ID from the translator of the IC that includes that driver and accessing the portion of the memory connected to that IC that is identified by that physical portion ID.

2. The memory circuits defined in claim 1 wherein at least one of ICs includes circuitry for receiving a request from an external source for a block identified by the global ID of that requested block, and wherein the logic block manager of that IC includes circuitry for using the global ID of the requested block to determine the node ID and the logical block number of the requested block.

3. The memory circuits defined in claim 2 wherein if the circuitry for using determines that the node ID of the requested block is the node ID of the IC that includes that circuitry for using, then the logic block manager circuitry of that IC applies the logical block number of the requested block to the translator of that IC.

4. The memory circuits defined in claim 2 wherein if the circuitry for using determines that the node ID of the requested block is not the node ID of the IC that includes that circuitry for using, then the logic block manager circuitry of that IC employs circuitry for causing that IC to route data for the request to at least one other of the ICs.

5. The memory circuits defined in claim 4 wherein the circuitry for causing uses at least one of the inter-IC connections to route data for the request to at least one other of the ICs.

6. The memory circuits defined in claim 4 wherein the circuitry for causing is responsive to node ID data in the request to select a route for the request to at least one other of the ICs.

7. The memory circuits defined in claim 6 wherein the circuitry for causing is additionally responsive to data, stored in the IC that includes that circuitry for causing, indicative of topology of the ICs and the inter-IC connections.

8. The memory circuits defined in claim 4 wherein, when the request reaches the other IC (“

the reading IC”

) having the node ID of the requested block, the logic block manager of the reading IC applies the logic block number of the requested block to the translator of the reading IC.

9. The memory circuits defined in claim 8 wherein the driver of the reading IC reads the requested data from the memory circuitry connected to the reading IC so that the reading IC routes that data back to the IC that received the request from the external source.

10. The memory circuits defined in claim 1 wherein each of the ICs (“

the source IC”

) includes circuitry for transferring a block (“

the transferred block”

) accessed by the driver of the source IC to another of the ICs (“

the destination IC”

) for storage in the memory circuitry connected to the destination IC.

11. The memory circuits defined in claim 10 wherein the circuitry for transferring employs the inter-IC connections.

12. The memory circuits defined in claim 10 further comprising:

circuitry for updating the mapping of the translator of the source IC to delete the logical block number of the transferred block, and for updating the mapping of the translator of the destination IC to add the logical block number of the transferred block.

13. The memory circuits defined in claim 10 further comprising:

circuitry for changing the node ID of the transferred block in the block manager in all of the ICs from the node ID of the source IC to the node ID of the destination IC.

14. The memory circuits defined in claim 1 wherein each of the ICs (“

the source IC”

) further includes;

circuitry for maintaining a count of how many times each of the other ICs requests a respective block contained in the memory circuit that is connected to the source IC; and

circuitry for transferring a block (“

the transferred block”

), for which the count for one of the other ICs (“

the destination IC”

) exceeds a threshold value, from the memory circuit connected to the source IC to the memory circuit connected to the destination IC.

15. The memory circuits defined in claim 14 wherein the circuitry for transferring employs the inter-IC connections.

16. The memory circuits defined in claim 14 further comprising:

circuitry for updating the mapping of the translator of the source IC to delete the logical block number of the transferred block, and for updating the mapping of the translator of the destination IC to add the logical block number of the transferred block.

17. The memory circuits defined in claim 14 further comprising:

circuitry for changing the node ID of the transferred block in the block manager in at least one of the ICs from the node ID of the source IC to the node ID of the destination IC.

18. Managing access to a plurality of memory circuits, each of which is connected to a respective one of a plurality of integrated circuits (“

ICs”

), one of the ICs being connected to at least one of the other ICs by inter-IC connections so that one IC exchanges blocks of memory circuit data with another IC via the inter-IC connections, each of the ICs (“

the source IC”

) including a memory manager comprising;

circuitry for maintaining a count of how many times a given IC requests at least one block contained in the memory circuit that is connected to the source IC; and

circuitry for transferring a block (“

the transferred block”

), for which the count for one of the other ICs (“

the destination IC”

) exceeds a threshold value, from the memory circuit connected to the source IC to the memory circuit connected to the destination IC.

19. The memory manager defined in claim 18 wherein the circuitry for transferring employs the inter-IC connections.

20. The memory manager defined in claim 18 wherein an IC further comprises:

circuitry for maintaining a record of where a given block is currently stored, said record including a node identification (“

ID”

) which identifies the IC that is connected to the memory circuit in which a given block is currently stored.