Dual function compatible non-volatile memory device
First Claim
1. A method for setting an operating mode of a memory device, the method comprising:
- powering up the memory device and detecting a power supply voltage reaching a predetermined level;
detecting a voltage of a port when the power supply voltage reaches the predetermined level,responding to the voltage of the port to provide a response after the memory device has completed power up; and
setting an operation mode of circuitry of the memory device in response to the response.
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Accused Products
Abstract
A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.
105 Citations
17 Claims
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1. A method for setting an operating mode of a memory device, the method comprising:
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powering up the memory device and detecting a power supply voltage reaching a predetermined level; detecting a voltage of a port when the power supply voltage reaches the predetermined level, responding to the voltage of the port to provide a response after the memory device has completed power up; and setting an operation mode of circuitry of the memory device in response to the response. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification