High sensitivity GPS receiver

• US 8,270,457 B2
• Filed: 06/25/2008
• Issued: 09/18/2012
• Est. Priority Date: 06/27/2007
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm Atheros Incorporated (Qualcomm, Inc.)
• Inventors: Sun, Qinfang, Yeh, Wen-Chang, Chen, Ho-Chung
• Primary Examiner(s): Yu, Lihong
• Application Number:
  US12/145,918
• Publication Number:
  US 20090079627A1
• Time in Patent Office: 1,546 Days
• Field of Search: 375/150
• US Class Current: 375/150
• CPC Class Codes: G01S 19/24 Acquisition or tracking or demodulation of signals transmitted by the system synchronisation aspects of direct sequence spread spectrum modulation H04B1/7073
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/36 relating to the receiver frond end
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: H04L 7/0016 correction of synchronization errors

Abstract

A high sensitivity GPS receiver includes an acquisition engine and a tracking engine. The acquisition engine processes GPS satellite data at data rate that is substantially equal to twice the coarse acquisition (CA) code chip rate. This data rate advantageously enables the acquisition engine to process GPS satellite data with relatively less hardware area than traditional GPS acquisition approaches. In one embodiment, the high efficiency acquisition engine may be over-clocked, thereby allowing different phases of a CA code to be correlated quickly. The tracking engine can advantageously processes GPS satellite data at a data rate that does not have an integer relationship to the CA code chip rate.

Claims

1. A configurable correlator for an acquisition channel in a GPS receiver, the configurable correlator comprising:

a pre-summer for receiving resampled digital baseband data, the pre-summer consisting of;

a mixer configured to mix the resampled digital baseband data and a Doppler frequency;

a flip-flop receiving an output of the mixer; and

a first adder receiving outputs of the flip-flop and the mixer;

a delay line for receiving an output of the first adder, the delay line including a plurality of registers connected in a daisy-chain and a plurality of tap points provided between certain of the plurality of registers;

a plurality of correlation multipliers for receiving outputs of the plurality of tap points, wherein a number of the plurality of correlation multipliers is one-half a number of the plurality of registers;

an adder tree for receiving outputs from the plurality of correlation multipliers;

an second adder for receiving an output of the adder tree; and

a correlation memory for receiving an output of the second adder and providing an input to the second adder.

2. The configurable correlator of claim 1, further comprising a code memory, wherein each correlation multiplier further receives a coarse acquisition code stored in the code memory.

3. A configurable correlator for an acquisition channel in a GPS receiver, the configurable correlator comprising:

a pre-summer consisting of a mixer for mixing resampled digital baseband data and an estimated Doppler frequency, a register coupled to an output of the mixer, and a first adder coupled to an output of the mixer and an output of the register;

a delay line coupled to an output of the first adder, the delay line including a plurality of registers connected in a daisy-chain and a plurality of tap points, wherein one tap point is provided after a first register of the plurality of registers and thereafter other tap points are provided after every other register of the plurality of registers;

a plurality of correlation multipliers, each correlation multiplier coupled to a tap point;

an adder tree coupled to outputs of the plurality of correlation multipliers;

a second adder coupled to an output of the adder tree; and

a correlation memory coupled to an output of the second adder, wherein the second adder is further coupled to an output of the correlation memory.

4. The configurable correlator of claim 3, further comprising a code memory, wherein each correlation multiplier further receives a coarse acquisition code stored in the code memory.

5. The configurable correlator of claim 3, wherein a final stage of the adder tree is configured to a width that accommodates a full sum with a desired precision.

6. A configurable correlator for an acquisition channel in a GPS receiver, the configurable correlator comprising:

a first processing stage including a pre-summer and a delay line section, wherein the pre-summer provides an output to the delay line section;

one or more subsequent processing stages, each subsequent processing stage including a pre-summer, a stage multiplexer, and a delay line section,

wherein each stage multiplexer receives an output of a corresponding pre-summer and provides an output to a corresponding delay line section,

wherein a stage multiplexer in a first subsequent processing stage further receives an output of the delay line section of the first processing stage, and in any other subsequent processing stage, a stage multiplexer further receives an output of a delay line section from a corresponding processing stage,

wherein each pre-summer of the first and subsequent processing stages consists of a mixer receiving resampled digital baseband data and an estimated Doppler frequency, a register receiving an output of the mixer, and a first adder receiving an output of the mixer and an output of the register,

wherein each delay line section of the first and subsequent processing stages includes a plurality of registers connected in a daisy-chain and a plurality of tap points between certain of the plurality of registers,

a plurality of correlation multipliers, each correlation multiplier coupled to a tap point;

a plurality of adder tree sections, each adder tree section receiving outputs from a corresponding set of correlation multipliers;

a plurality of multiplexers, each multiplexer for receiving an output of a corresponding adder tree section;

a multiplexer selector for receiving an output from each of the plurality of multiplexers;

an additional adder tree section for receiving an output from each of the plurality of multiplexers;

a two-to-one multiplexer for receiving outputs from the multiplexer selector and the additional adder tree section;

a final adder for receiving an output of the two-to-one multiplexer; and

a correlation memory for receiving an output of the final adder, wherein an output of the correlation memory is provided to the final adder.

7. The configurable correlator of claim 6, further comprising a code memory, wherein each correlation multiplier further receives a coarse acquisition code stored in the code memory.

8. The configurable correlator of claim 7, wherein the configurable correlator has 16 processing stages, and wherein each delay line section includes 33 tap points.

9. A high-sensitivity GPS receiver comprising:

an antenna;

an analog section for receiving an output of the antenna;

a digital section for receiving an output of the analog section; and

a processor for receiving an output of the digital section,

wherein the digital section includes a plurality of acquisition channels, at least one acquisition channel comprising a configurable correlator, the configurable correlator comprising;

a pre-summer for receiving resampled digital baseband data, the pre-summer consisting of;

a mixer configured to mix the resampled digital baseband data and a Doppler frequency;

a flip-flop receiving an output of the mixer; and

a first adder receiving outputs of the flip-flop and the mixer;

a delay line for receiving an output of the first adder, the delay line including a plurality of registers connected in a daisy-chain and a plurality of tap points provided between certain of the plurality of registers;

a plurality of correlation multipliers for receiving outputs of the plurality of tap points, wherein a number of the plurality of correlation multipliers is one-half a number of the plurality of registers;

an adder tree for receiving outputs from the plurality of correlation multipliers;

an second adder for receiving an output of the adder tree; and

a correlation memory for receiving an output of the second adder and providing an input to the second adder.

10. A high-sensitivity GPS receiver comprising:

an antenna;

an analog section for receiving an output of the antenna;

a digital section for receiving an output of the analog section; and

a processor for receiving an output of the digital section,

wherein the digital section includes a plurality of acquisition channels, at least one acquisition channel comprising a configurable correlator, the configurable correlator comprising;

a pre-summer consisting of a mixer for mixing resampled digital baseband data and an estimated Doppler frequency, a register coupled to an output of the mixer, and a first adder coupled to an output of the mixer and an output of the register;

a delay line coupled to an output of the first adder, the delay line including a plurality of registers connected in a daisy-chain and a plurality of tap points, wherein one tap point is provided after a first register of the plurality of registers and thereafter other tap points are provided after every other register of the plurality of registers;

a plurality of correlation multipliers, each correlation multiplier coupled to a tap point;

an adder tree coupled to outputs of the plurality of correlation multipliers;

a second adder coupled to an output of the adder tree; and

a correlation memory coupled to an output of the second adder, wherein the second adder is further coupled to an output of the correlation memory.