Adaptive equalizer circuit
First Claim
1. An adaptive equalizer circuit, comprising:
- an equalizer circuit configured to produce an output data signal by correcting an input data signal waveform for each unit time in response to an equalizing factor;
a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at a predetermined timing indicated by a clock signal synchronized with the output data signal;
a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½
unit time away from the predetermined timing indicated by the clock signal; and
a control circuit configured to detect, multiple times, a predetermined data pattern having consecutive data items of a first logic value followed by a data item of a second logic value and further followed by a data item of the first logic value, and to adjust the equalizing factor such that a value of a detection result obtained by the data detecting circuit and a value of a detection result obtained by the boundary detecting circuit for the data item of the second logic value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times, the equalizing factor being adjusted such that a data width of the predetermined data pattern becomes equal to one unit time.
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Accused Products
Abstract
An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½ unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.
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Citations
10 Claims
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1. An adaptive equalizer circuit, comprising:
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an equalizer circuit configured to produce an output data signal by correcting an input data signal waveform for each unit time in response to an equalizing factor; a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at a predetermined timing indicated by a clock signal synchronized with the output data signal; a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½
unit time away from the predetermined timing indicated by the clock signal; anda control circuit configured to detect, multiple times, a predetermined data pattern having consecutive data items of a first logic value followed by a data item of a second logic value and further followed by a data item of the first logic value, and to adjust the equalizing factor such that a value of a detection result obtained by the data detecting circuit and a value of a detection result obtained by the boundary detecting circuit for the data item of the second logic value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times, the equalizing factor being adjusted such that a data width of the predetermined data pattern becomes equal to one unit time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An adaptive equalizer circuit, comprising:
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an equalizer circuit configured to produce an output data signal by correcting an input data signal waveform for each unit time in response to an equalizing factor; a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at a predetermined timing indicated by a clock signal synchronized with the output data signal; a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½
unit time away from the predetermined tinning indicated by the clock signal; anda control circuit configured to detect, multiple times, a predetermined data pattern having consecutive data items of a first logic value followed by a data item of a second logic value, and to adjust the equalizing factor such that a value of a detection result obtained by the data detecting circuit and a value of a detection result obtained by the boundary detecting circuit for the data item of the second logic value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times, wherein the control circuit is configured to assign a first value to a case of the values of the detection results being equal to each other, to assign a second value responsive to the first value to a case of the values of the detection results being different from each other, to obtain an accumulated sum of the first value and the second value for the multiple-time detections, and to adjust the equalizing factor in response to the accumulated sum, and wherein the control circuit is configured to repeatedly obtain the accumulated sum, to repeatedly adjust the equalizing factor in response to an absolute value of the accumulated sum, and to allow a direction of change of the equalizing factor to be set when the absolute value consecutively assumes a same value.
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Specification