System and method for video and audio encoding on a single chip

• US 8,270,479 B2
• Filed: 06/11/2002
• Issued: 09/18/2012
• Est. Priority Date: 04/06/1999
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Morad, Amir, Yavits, Leonid, Oxman, Gadi, Spektor, Evgeny, Chernov, Gregory, Khrapkovsky, Michael
• Primary Examiner(s): VO, TUNG T
• Application Number:
  US10/170,019
• Publication Number:
  US 20030108105A1
• Time in Patent Office: 3,752 Days
• Field of Search: 37524001-24028, 345/204, 709/247, 710/20, 725/95, 348/14.08, 348/14.13, 348/558, 348/416.1, 370/395.2
• US Class Current: 375/240.12
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/226 Characteristics of the server or Internal components of the server
• CPC Class Codes: H04N 21/236 Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream multiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/2368 Multiplexing of audio and video streams
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams
• CPC Class Codes: H04N 7/52 Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal assembling of a multiplex stream by combining a video stream with other content or additional data, remultiplexing of multiplex streams, insertion of stuffing bits into the multiplex stream, assembling of a packetised elementary stream at server side H04N21/236; disassembling of a multiplex stream, remultiplexing of multiplex streams, extraction or processing of Service Information, disassembling of packetised elementary stream at client side H04N21/434

Abstract

An apparatus is disclosed for performing real time video/audio encoding on a single chip. Within the single chip, a video encoder generates encoded video data from uncompressed video data and an audio encoder generates encoded audio data from uncompressed audio data. A mux processor within the single chip generates an output stream of encoded data from the encoded video data and the encoded audio data.

Claims

1. A single-chip audio/video encoder device comprising, on a single integrated circuit:

first encoder circuitry, second encoder circuitry, multiplexer circuitry, controller circuitry, and at least one bus interface;

wherein the first encoder circuitry comprises;

a first video encoder that receives first uncompressed video data from a first video source external to the device and produces first compressed video,

a first audio encoder that receives first uncompressed audio data from a first audio source external to the device, and that produces first compressed audio, and

a first memory interface that interfaces directly with first storage external to the device;

wherein the second encoder circuitry comprises;

a second video encoder that receives second uncompressed video data from a second video source external to the device and that produces second compressed video,

a second audio encoder that receives second uncompressed audio data from a second audio source external to the device and that produces second compressed audio, and

a second memory interface that interfaces directly with second storage external to the device;

wherein the multiplexer circuitry operating in a first mode,

multiplexes the first compressed video, the first compressed audio, the second compressed video, and the second compressed audio to form a first multiplexed stream operably coupled via a first output to circuitry external to the device;

wherein the multiplexer circuitry operating in a second mode,

multiplexes the first compressed video and the first compressed audio to form the first multiplexed stream operably coupled via the first output to circuitry external to the device, and

multiplexes the second compressed video and the second compressed audio to form a second multiplexed stream operably coupled via a second output to circuitry external to the device;

wherein the controller circuitry synchronizes operation of the first encoder circuitry, the second encoder circuitry, and the multiplexer circuitry; and

wherein the at least one bus interface operably couples the controller circuitry and at least one processor external to the device.

2. The device according to claim 1, wherein the first video encoder and the second video encoder perform luminance and chrominance filtering.

3. The device according to claim 1, wherein the first storage and the second storage comprise synchronous dynamic random access memory.

4. The device according to claim 1, wherein the controller circuitry comprises a first controller that controls operation of the first video encoder, the first audio encoder, and the first memory interface, and a second controller that controls operation of the second video encoder, the second audio encoder, and the second memory interface.

5. The device according to claim 4, wherein the at least one bus interface comprises a first bus interface that operably couples the first controller and the at least one processor external to the device, and a second bus interface that operably couples the second controller and the at least one processor external to the device.

6. The device according to claim 4, wherein the at least one bus interface is configurable as a peripheral component interconnect bus interface.

7. The device according to claim 4, wherein the at least one bus interface is configurable to transfer one or both of the first multiplexed stream and the second multiplexed stream to memory of the at least one processor external to the device, as a bus master using direct memory access.

8. The device according to claim 4, wherein the at least one bus interface is configurable as a generic host interface.

9. The device according to claim 1, wherein the first video encoder, the first audio encoder, the second video encoder, the second audio encoder, and the multiplexer circuitry execute microcode instructions received by the device via the at least one bus interface.

10. The device according to claim 1, wherein each of the first uncompressed audio data and the second uncompressed audio data represent two audio channels.

11. The device according to claim 1, wherein the first video encoder and the second video encoder each comprise a motion estimation processor comprising a plurality of search processors for performing motion analysis.

12. The device according to claim 11, wherein the plurality of search processors operate in parallel, each upon a different portion of a macroblock.

13. The device according to claim 11, wherein the plurality of search processors operate in parallel upon a single macroblock, each search processor operating at a different one of a plurality of resolutions.

14. A single-chip audio/video encoder device comprising, on a single integrated circuit:

first encoder circuitry, second encoder circuitry, multiplexer circuitry, controller circuitry, and at least one bus interface;

wherein the first encoder circuitry comprises;

a first video encoder that receives first uncompressed video data from a first video source external to the device and produces first compressed video, the first video encoder comprising a first motion estimation processor comprising a first plurality of search processors for performing motion analysis, and

a first audio encoder that receives first uncompressed audio data from a first audio source external to the device, and that produces first compressed audio;

wherein the second encoder circuitry comprises;

a second video encoder that receives second uncompressed video data from a second video source external to the device and that produces second compressed video, the second video encoder comprising a second motion estimation processor comprising a second plurality of search processors for performing motion analysis, and

a second audio encoder that receives second uncompressed audio data from a second audio source external to the device and that produces second compressed audio;

wherein the multiplexer circuitry operates in a first mode that multiplexes the first compressed video, the first compressed audio, the second compressed video, and the second compressed audio to produce a first multiplexed stream coupled via a first output to circuitry external to the device, and operates in a second mode that multiplexes the first compressed video and the first compressed audio to produce the first multiplexed stream coupled via the first output to circuitry external to the device and multiplexes the second compressed video and the second compressed audio to produce a second multiplexed stream coupled via a second output to circuitry external to the device;

wherein the controller circuitry synchronizes operation of the first encoder circuitry, the second encoder circuitry, and the multiplexer circuitry; and

wherein the at least one bus interface operably couples the controller circuitry and at least one processor external to the device.

15. The device according to claim 14, wherein the device further comprises a first memory interface that interfaces the first encoder circuitry with first storage external to the device, and a second memory interface that interfaces the second encoder circuitry with second storage external to the device.

16. The device according to claim 15, wherein the first storage and the second storage comprise synchronous dynamic random access memory.

17. The device according to claim 14, wherein the first video encoder and the second video encoder perform luminance and chrominance filtering.

18. The device according to claim 14, wherein the controller circuitry comprises a first controller that controls operation of the first video encoder and the first audio encoder, and a second controller that controls operation of the second video encoder and the second audio encoder.

19. The device according to claim 14, wherein the at least one bus interface comprises a first bus interface that operably couples the first controller and the at least one processor external to the device, and a second bus interface that operably couples the second controller and the at least one processor external to the device.

20. The device according to claim 14, wherein the at least one bus interface is configurable as a peripheral component interconnect bus interface.

21. The device according to claim 14, wherein the at least one bus interface is configurable to transfer one or both of the first multiplexed stream and the second multiplexed stream to memory of the at least one processor external to the device, as a bus master using direct memory access.

22. The device according to claim 14, wherein the first video encoder, the first audio encoder, the second video encoder, the second audio encoder, and the multiplexer circuitry execute microcode instructions received by the device via the at least one bus interface.

23. The device according to claim 14, wherein each of the first uncompressed audio data and the second uncompressed audio data represent two audio channels.

24. The device according to claim 14, wherein search processors of the first plurality of search processors operate in parallel, each upon a different portion of a macroblock.

25. The device according to claim 14, wherein search processors of the first plurality of search processors operate in parallel upon a single macroblock, each search processor operating at a different one of a plurality of resolutions.