Interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage

• US 8,271,055 B2
• Filed: 11/21/2002
• Issued: 09/18/2012
• Est. Priority Date: 11/21/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Carballo, Juan-Antonio, Burns, Jeffrey L.
• Primary Examiner(s): Yun, Eugene
• Application Number:
  US10/302,494
• Publication Number:
  US 20040203477A1
• Time in Patent Office: 3,589 Days
• Field of Search: 455/574, 455/69, 455/115.1, 455/115.2, 455/115.3, 455/127.5, 455/343.1, 455/127.1, 455/127.4
• US Class Current: 455/574
• CPC Class Codes: H04W 52/04 TPC

Abstract

An interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage reduces power consumption when interface conditions will support a transceiver having reduced complexity. The power supply voltage of the reduced complexity logic is then reduced if the lowered complexity will support a lower power supply voltage. The reduced complexity in combination with a reduced power supply voltage decreases power consumption to a greater degree than reducing transceiver complexity alone.

The complexity of processing blocks within the receiver and/or transmitter are adjusted in conformity with one or more selection signals and an operating voltage level is selected in accordance with the requirements of the reduced complexity circuit. An interface quality measurement circuit may provide the selection signal, so that the transceiver complexity is adjusted in response to measured interface conditions or an external pin or register bit may be coupled to a select input.

Claims

1. A transceiver for interconnecting electronic devices, comprising:

at least one interface circuit including an internal processing block having selectable complexity, said interface circuit including at least one electrical terminal adapted for connection to an interconnect bus bearing one or more interface signals to a remote transceiver;

a power supply circuit coupled to said internal processing block and having a selectable output voltage level;

a select input coupled to said at least one interface circuit for receiving a selection signal, whereby a level of complexity of said processing block is selected by a logic state of said select input and wherein a power supply voltage level of said power supply circuit is further selected in conformity with said select input; and

a communication link for transmitting a state of said select input to a remote transceiver over said interconnect bus.

2. A method of controlling power consumption in an interface transceiver, comprising:

receiving an indication of that power consumption of said interface transceiver may be reduced;

in response to said receiving, selecting a complexity of said receiver;

in further response to said receiving, selecting a power supply voltage level of at least one internal processing block of said interface transceiver;

operating said interface transceiver with said at least one internal processing block operating at said selected power supply voltage level to communicate at least one signal to a remote transceiver over an interconnect bus including at least one signal conductor;

measuring, within said interface transceiver, a quality of an interface signal carried on said interconnect bus;

determining whether or not said quality is above a threshold level; and

in response to determining that said quality is above a threshold level, generating said indication.

3. The method of claim 2, further comprising communicating a state of said indication to a remote transceiver.