Virtual supercomputer

• US 8,271,259 B2
• Filed: 06/28/2010
• Issued: 09/18/2012
• Est. Priority Date: 04/09/2003
• Status: Active Grant

• Current Assignee: Veriscape, Inc.
• Original Assignee: Veriscape, Inc.
• Inventors: Berkowitz, Gary Charles, Wurtz, Charles Christopher
• Primary Examiner(s): JONES, HUGH M
• Application Number:
  US12/824,579
• Publication Number:
  US 20110004566A1
• Time in Patent Office: 813 Days
• Field of Search: 703 21- 22, 703/23
• US Class Current: 703/23
• CPC Class Codes: G06F 16/22 Indexing; Data structures therefor; Storage structures
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

The virtual supercomputer is an apparatus, system and method for generating information processing solutions to complex and/or high-demand/high-performance computing problems, without the need for costly, dedicated hardware supercomputers, and in a manner far more efficient than simple grid or multiprocessor network approaches. The virtual supercomputer consists of a reconfigurable virtual hardware processor, an associated operating system, and a set of operations and procedures that allow the architecture of the system to be easily tailored and adapted to specific problems or classes of problems in a way that such tailored solutions will perform on a variety of hardware architectures, while retaining the benefits of a tailored solution that is designed to exploit the specific and often changing information processing features and demands of the problem at hand.

Claims

1. A system to determine a solution for a problem including a solution space represented by one or more nodes, said system comprising:

a computer system, including at least one processor and an operating system to control operation of said computer system, to dynamically configure and emulate a hardware architecture of a processing system that processes said one or more nodes to determine said solution for said problem, wherein at least one of said nodes includes data for said problem and said computer system further includes;

a virtual machine unit to emulate said hardware architecture and manage said nodes within said solution space, wherein said hardware architecture is designed to process said nodes;

a virtual operating system to configure said virtual machine unit and to control operation of said virtual machine unit to emulate said hardware architecture based on parameters, said virtual operating system including;

an instantiation engine to create and to delete said nodes;

a configuration engine to configure said nodes of said solution space in a topology to determine said solution for said problem;

a population engine to store and to evaluate said data for said problem within said nodes;

a navigation engine to traverse said topology and to process selected ones of said nodes based on said parameters to determine said solution; and

an evolution engine to update said nodes and said topology based on said parameters.

2. The system of claim 1, wherein said emulated hardware architecture is dynamically reconfigurable.

3. The system of claim 2 wherein said emulated hardware architecture comprises reconfigurable elements including one or more of:

a type and number of units in said emulated hardware architecture;

a structure of memory;

registers;

data words;

index words;

machine instructions;

node structure and topology; and

a configuration unit to configure configurable elements of said emulated hardware architecture.

4. The system of claim 3, wherein a configuration of said dynamically reconfigurable hardware architecture includes one or more of an instantiation unit to create and to delete said nodes, a population unit to store and to evaluate data within said nodes, a navigation unit to traverse said topology and to retrieve information from selected nodes, a node counter, and an arithmetic logic unit to perform arithmetic operations.

5. The system of claim 1, wherein said computer system includes one or more of a conventional computing platform and a virtual-supercomputing platform.

6. The system of claim 1, wherein said computer system includes one or more of a Von Neumann computing platform and a Non-Von Neumann computing platform.

7. A program product apparatus comprising:

a computer useable memory device with computer program logic stored therein, the computer program logic, when executed by a computer system, causes the computer system to determine a solution for a problem including a solution space represented by one or more nodes and said computer program logic includes;

a virtual machine unit to dynamically configure and emulate a hardware architecture of a processing system that processes said one or more nodes to determine said solution for said problem, wherein at least one of said nodes includes data for said problem;

a virtual operating system to configure said virtual machine unit and to control operation of said virtual machine unit to emulate said hardware architecture based on parameters, said virtual operating system including;

an instantiation engine to create and to delete said nodes;

a configuration engine to configure said nodes of said solution space in a topology to determine said solution for said problem;

a population engine to store and to evaluate said data for said problem within said nodes;

a navigation engine to traverse said topology and to process selected ones of said nodes based on said parameters to determine said solution; and

an evolution engine to update said nodes and said topology based on said parameters.

8. The apparatus of claim 7, wherein said emulated hardware architecture is dynamically reconfigurable.

9. The apparatus of claim 8, wherein said emulated hardware architecture comprises reconfigurable elements including one or more of:

a type and number of units in said emulated hardware architecture;

a structure of memory;

registers;

data words;

index words;

machine instructions;

node structure and topology; and

a configuration unit to configure configurable elements of said emulated hardware architecture.

10. The apparatus of claim 9, wherein a configuration of said dynamically reconfigurable hardware architecture includes one or more of an instantiation unit to create and to delete said nodes, a population unit to store and to evaluate data within said nodes, a navigation unit to traverse said topology and to retrieve information from selected nodes, a node counter, and an arithmetic logic unit to perform arithmetic operations.

11. The apparatus of claim 7, wherein said computer system includes one or more of a conventional computing platform and a virtual-supercomputing platform.

12. The apparatus of claim 7, wherein said computer system includes one or more of a Von Neumann computing platform and a Non-Von Neumann computing platform.

13. A method of determining, via a computer system, a solution for a problem including a solution space represented by one or more nodes, said method comprising:

(a) dynamically configuring and emulating, via a computer system, a hardware architecture of a processing system that processes said one or more nodes to determine said solution for said problem, wherein at least one of said nodes includes data for said problem;

(b) configuring and controlling emulation of said hardware architecture based on parameters, wherein step (b) further includes;

(b.1) creating and deleting said nodes;

(b.2) configuring said nodes of said solution space in a topology to determine said solution for said problem;

(b.3) storing and evaluating said data for said problem within said nodes;

(b.4) traversing said topology and processing selected ones of said nodes based on said parameters to determine said solution; and

(b.5) updating said nodes and said topology based on said parameters.

14. The method of claim 13, wherein said emulated hardware architecture is dynamically reconfigurable.

15. The method of claim 14, wherein said emulated hardware architecture comprises reconfigurable elements including one or more of:

a type and number of units in said emulated hardware architecture;

a structure of memory;

registers;

data words;

index words;

machine instructions;

node structure and topology; and

a configuration unit to configure configurable elements of said emulated hardware architecture.

16. The method of claim 15, wherein a configuration of said dynamically reconfigurable hardware architecture includes one or more of an instantiation unit to create and to delete said nodes, a population unit to store and to evaluate data within said nodes, a navigation unit to traverse said topology and to retrieve information from selected nodes, a node counter, and an arithmetic logic unit to perform arithmetic operations.

17. The method of claim 13, wherein said computer system includes one or more of a conventional computing platform and a virtual-supercomputing platform.

18. The method of claim 13, wherein said computer system includes one or more of a Von Neumann computing platform and a Non-Von Neumann computing platform.