Hardware automatic performance state transitions in system on processor sleep and wake events

• US 8,271,812 B2
• Filed: 04/07/2010
• Issued: 09/18/2012
• Est. Priority Date: 04/07/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: de Cesare, Josh P., Cho, Jung Wook, Takayanagi, Toshi, Millet, Timothy J.
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US12/756,006
• Publication Number:
  US 20110252251A1
• Time in Patent Office: 895 Days
• Field of Search: 713/300, 713/320, 713/323, 713/324, 345/52, 345/211, 365/227, 455/574, 719/321
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Claims

1. An integrated circuit comprising:

at least one processor;

one or more registers programmable to indicate one or more performance states; and

a control circuit coupled to the one or more registers and the processor, wherein the control circuit is configured to detect that the processor is entering a sleep state, and wherein the control circuit is configured to change a performance state of at least one performance domain in the integrated circuit to a first performance state of the one or more performance states in response to the processor entering the sleep state, and wherein the control circuit is configured to detect that the processor is exiting the sleep state, and wherein the control circuit is configured to change the performance state of at least one performance domain in the integrated circuit to a second performance state of the one or more performance states in response to the processor exiting the sleep state, and wherein the second performance state differs from a third performance state that was in effect prior to the processor entering the sleep state.

2. The integrated circuit as recited in claim 1 wherein the at least one performance domain includes the processor.

3. The integrated circuit as recited in claim 1 wherein the control circuit is configured to record a first timestamp indicating a time at which the change to the first performance state is completed, and wherein the control circuit is configured to record a second timestamp indicating a time at which the change to the second performance state is completed.

4. A non-transitory computer accessible storage medium storing a plurality of instructions which, when executed:

monitor activity in a plurality of components of a system, wherein the components are included in one or more performance domains, and wherein the system comprises at least one processor;

program a plurality of registers corresponding to one or more performance domains of a system to indicate a first performance state for a first performance domain of the one or more performance domains, wherein the system is to establish the first performance state for the first performance domain responsive to the processor entering a low performance state; and

program a second plurality of registers corresponding to the one or more performance domains of the system to indicate a second performance state for the first performance domain, wherein the system is to establish the second performance state for the first performance domain responsive to the processor exiting the low performance state, and wherein the first performance domain includes the processor, and wherein the first performance state differs from a third performance state of the first domain prior to the processor entering the low performance state.

5. The non-transitory computer accessible storage medium as recited in claim 4 wherein the plurality of instructions are executed responsive to a request to activate a first component of the plurality of components, and wherein monitoring the activity includes recording an indication of the activation of the first component.

6. The non-transitory computer accessible storage medium as recited in claim 5 wherein the plurality of instructions are executed responsive to a request to deactivate the first component, and wherein monitoring the activity includes recording an indication of the deactivation of the first component.

7. The non-transitory computer accessible storage medium as recited in claim 4 wherein the first performance domain corresponds to one or more components that are active during a time that the processor is in the low performance state.

8. An apparatus comprising:

a plurality of components, each component included in one of a plurality of performance domains; and

a power management unit configured to establish a performance state in each of the plurality of performance domains, and wherein the power management unit is configured to transition at least a first performance domain of the plurality of performance domains to a first performance state programmed into the power management unit responsive to a processor transitioning to a wakeup state, wherein the processor is transitioning from a sleep state, and wherein the wakeup state is different from a prior performance state at which the processor was operating prior to entering the sleep state.

9. The apparatus as recited in claim 8 wherein the power management unit is configured to transition each of the performance domains into a respective power state programmed into the power management unit responsive to the processor transitioning to the different performance state.

10. A method comprising:

a processor entering a sleep state in a system;

a power management unit causing a performance domain of the system to transition to a first performance state to operate during a time that the processor is in the sleep state, wherein the first performance state is programmable in the power management unit;

determining the first performance state to program into the power management unit responsive to monitoring operation of the system;

the power management unit detecting that the processor is exiting the sleep state; and

the power management unit further causing the performance domain to transition to a second performance state to operate subsequent to the processor exiting the sleep state, wherein the second performance state is programmed in the power management unit, wherein the second performance state is different from a third performance state for the performance domain prior to the processor entering the sleep state.

11. The method as recited in claim 10 further comprising:

continuing to monitor the system; and

reprogramming the power management unit with a fourth performance state responsive to the continued monitoring.