Information handling system with processing system, low-power processing system and shared resources

• US 8,271,817 B2
• Filed: 09/23/2011
• Issued: 09/18/2012
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Belt, Steven L., Sultenfuss, Andrew T.
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US13/242,635
• Publication Number:
  US 20120013795A1
• Time in Patent Office: 361 Days
• Field of Search: 710300-304, 710/306, 710/310, 713/300, 713/212
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.

Claims

1. An information handling system comprising:

a processing system configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system;

a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system; and

a chipset including a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system,

wherein the power system is further configured to enable a power rail of a first power subsystem and a power rail of a second power subsystem in response to an operating state of the processing system and operating state of the low-power processing system.

2. The information handling system of claim 1, further comprising a low-power processing module including a low power processor of the low-power processing system, wherein the low-power processing module is accessible to the chipset during operation of the processing system.

3. The information handling system of claim 1, further comprising:

wherein the chipset includes the low-power processing system;

wherein the power system is operable to enable the processing system separate from the low-power processing system; and

wherein the power system is further operable to enable the low-power processing system separate from the processing system.

4. The information handling system of claim 1, further comprising:

a low-power processing module externally coupled to the chipset;

a video processing resource within the chipset and accessible to the processing system during operation of the processing system;

wherein the video processing resource is accessible to the low-power processing module during operation of the low-power processing system and the reduced operating state of the processing system;

a power subsystem of the power system configured to enable a portion of the chipset; and

wherein the low-power processing system is configured to access the enabled portion of the chipset to output video using the shared resource of the processing system during the reduced operating state of the processing system.

5. The information handling system of claim 1, further comprising:

a video input source operably coupled to the chipset during operation of the low-power processing system;

a video output resource of the processing system configured to identify the video input source; and

wherein the video output resource is configured to process a video input from the video input source to a display format of the display.

6. The information handling system of claim 1, further comprising:

wherein the chipset includes a low power processor of the low-power processing system; and

a peripheral switching module integrated within the chipset and configured to couple an output of the chipset to the shared resource during use of the processor and the low power processor.

7. The information handling system of claim 3, further comprising:

a video processing resource within the chipset and accessible to the processing system during operation of the processing system; and

wherein the video processing resource is accessible to the low-power processing system during operation of the low-power processing system.

8. The information handling system of claim 5, further comprising a power subsystem configured to enable the video output resource.

9. The information handling system of claim 7, wherein the video processing resource includes:

a video raster coupled to the chipset and operable to be accessed as a shared video output resource; and

wherein the video raster is further accessible to the low-power processing system and the processing system to simultaneously output video of the low-power processing system and video of the processing system to a shared video display resource.

10. A chipset comprising:

a processor configured to access a shared resource of a processing system during operation of the processing system;

a power system configured to enable a powering of the shared resource during operation of the processing system and operation of a low-power processing system;

a video multiplexing layer powered by the power system, the video multiplexing layer configured to receive a processing system video input and a low-power processing system video input, and to up-scale a video output by combining the processing system video input with the low-power processing system video input prior to outputting the video output; and

a peripheral switching module configured to couple an output to the shared resource during use of processing system and the low-power processing system.

11. The chipset of claim 10, further comprising:

a low power processor subsystem power source configured to be enabled in response to enabling a low power processor of the low-power processing system separate from the processing system.

12. The chipset of claim 10, wherein the shared resource includes:

a video display accessible to the low-power processing system during operation of the low-power processing system; and

wherein the video display is accessible to the processing system during operation of the processing system.

13. The chipset of claim 10, wherein the processor is a part of the processing system.

14. The chipset of claim 10, further comprising a low power processor of the low-power processing system.

15. The chipset of claim 10, further comprising:

a low power processor of the low-power processing system; and

wherein the processor is a part of the processing system.

16. An information handling system comprising:

a processing system configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system;

a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system; and

a chipset including a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system,

wherein the chipset includes a low power processor of the low-power processing system; and

a peripheral switching module integrated within the chipset and configured to couple an output of the chipset to the shared resource during use of the processor and the low power processor.

17. The information handling system of claim 16, further comprising a low-power processing module including a low power processor of the low-power processing system, wherein the low-power processing module is accessible to the chipset during operation of the processing system.

18. The information handling system of claim 17, further comprising:

wherein the chipset includes the low-power processing system;

wherein the power system is operable to enable the processing system separate from the low-power processing system; and

wherein the power system is further operable to enable the low-power processing system separate from the processing system.

19. The information handling system of claim 18, further comprising:

a video processing resource within the chipset and accessible to the processing system during operation of the processing system; and

wherein the video processing resource is accessible to the low-power processing system during operation of the low-power processing system.

20. The information handling system of claim 19, wherein the video processing resource includes:

a video raster coupled to the chipset and operable to be accessed as a shared video output resource; and

wherein the video raster is further accessible to the low-power processing system and the processing system to simultaneously output video of the low-power processing system and video of the processing system to a shared video display resource.