Dynamic power control of a memory device thermal sensor

• US 8,272,781 B2
• Filed: 08/01/2006
• Issued: 09/25/2012
• Est. Priority Date: 08/01/2006
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nale, William H.
• Primary Examiner(s): VERBITSKY, GAIL KAPLAN
• Application Number:
  US11/497,946
• Publication Number:
  US 20080043556A1
• Time in Patent Office: 2,247 Days
• Field of Search: 374170-172, 374/178, 374/141, 374/173, 331/66, 365/211, 365/212, 326/93, 327/512, 327/513, 702130-136
• US Class Current: 374/178
• CPC Class Codes: G01K 7/425 Thermal management of integrated systems
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 11/3034 where the computing system component is a storage system, e.g. DASD based or network based digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3093 Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device thermal sensor. In some embodiments a memory device includes an on-die thermal sensor and enable logic to dynamically enable or disable the on-die thermal sensor. In some embodiments, the on-die thermal sensor senses thermal data responsive to a thermal data sense indication. The thermal data sense indication may be received subsequent to the expiration of a delay period.

Claims

1. A system comprising:

a memory controller including;

a storage element to store a delay value specifying a delay period; and

thermal sensor control logic coupled to the storage element, the thermal sensor control logic to send an enable indication from the memory controller, the thermal sensor control logic further to send a thermal data sense indication in response to an expiration of the specified delay period after the sending the enable indication;

a dynamic random access memory (DRAM) device coupled with the memory controller, the DRAM device including,

enable logic to receive the enable indication from the memory controller and to assert an enable signal in response to the enable indication; and

an on-die thermal sensor coupled with the enable logic, wherein the enable signal is to power on the on-die thermal sensor, wherein the thermal data sense indication is to trigger a measurement by the on-die thermal sensor, wherein the delay period is based upon a set-up time for allowing the on-die thermal sensor to stabilize after powering on.

2. The system of claim 1, wherein, the DRAM is an element of a memory module.

3. The system of claim 1, wherein the enable logic comprises:

a storage element to store the enable indication; and

an enable circuit to provide the enable signal to the on-die thermal sensor.

4. The system of claim 3, wherein the enable circuit is configured to receive, as an input, the enable indication and the thermal data sense indication.

5. The system of claim 1, wherein the thermal data sense indication is a memory interconnect impedance calibration command.

6. The system of claim 5, wherein the memory interconnect impedance calibration command is a ZQ calibration command.

7. The system of claim 3, wherein the enable indication comprises one or more bits of a mode register set (MRS) command.

8. The system of claim 3, wherein the storage element is at least a portion of a mode register.

9. A memory controller device comprising:

a storage element to store a delay value specifying a delay period based upon a set-up time for allowing an on-die thermal sensor of a memory device to stabilize after powering on, the memory controller to couple to the memory device; and

thermal sensor control logic coupled to the storage element, the thermal sensor control logic to send an enable indication from the memory controller to enable logic of the memory device, wherein the enable logic asserts an enable signal in response to the enable indication, the enable signal to power on the on-die thermal sensor, the thermal sensor control logic further to send a thermal data sense indication to trigger a measurement by the on-die thermal sensor, wherein the thermal data sense indication is sent in response to an expiration of the specified delay period after the sending the enable indication.

10. The memory controller device of claim 9, wherein the enable indication comprises one or more bits of a mode register set command.

11. The memory controller device of claim 9, wherein the thermal data sense indication includes a memory interconnect impedance calibration command.

12. The memory controller device of claim 11, wherein the memory interconnect impedance calibration command includes a ZQ calibration command.

13. The memory controller device of claim 9, wherein the delay period is less than a period between successive thermal readings by the on-die thermal sensor.

14. A method at a memory controller device, the method comprising:

storing a delay value specifying a delay period based upon a set-up time for allowing an on-die thermal sensor of a memory device to stabilize after powering on, wherein the memory controller is coupled to the memory device;

sending an enable indication from the memory controller to enable logic of the memory device, wherein the enable logic asserts an enable signal in response to the enable indication, the enable signal to power on the on-die thermal sensor; and

sending a thermal data sense indication to trigger a measurement by the on-die thermal sensor, wherein the thermal data sense indication is sent in response to an expiration of the specified delay period after the sending the enable indication.

15. The memory controller device of claim 14, wherein the enable indication comprises one or more bits of a mode register set command.

16. The memory controller device of claim 14, wherein the thermal data sense indication includes a memory interconnect impedance calibration command.

17. The memory controller device of claim 16, wherein the memory interconnect impedance calibration command includes a ZQ calibration command.

18. The memory controller device of claim 14, wherein the delay period is less than a period between successive thermal readings by the on-die thermal sensor.