Structure for flash memory cells
First Claim
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1. A semiconductor structure comprising:
- a semiconductor substrate;
a first floating gate on the semiconductor substrate, the floating gate having a concave side surface;
a first control gate on the first floating gate;
a first spacer adjacent to the first control gate;
a first word line adjacent a first side of the first floating gate with a first distance; and
an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side,wherein the concave side surface has a tip portion corresponding to a widest part of the floating gate and a recessed portion corresponding to a narrowest part of the floating gate, wherein the tip portion extends to be approximately vertically aligned with an outer surface of the first spacer.
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Abstract
A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.
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Citations
20 Claims
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1. A semiconductor structure comprising:
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a semiconductor substrate; a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side, wherein the concave side surface has a tip portion corresponding to a widest part of the floating gate and a recessed portion corresponding to a narrowest part of the floating gate, wherein the tip portion extends to be approximately vertically aligned with an outer surface of the first spacer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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forming a floating gate layer above a semiconductor substrate; forming a control gate on the first floating gate; forming a first spacer adjacent the first control gate; etching the floating gate layer using a two-step etch to form a first floating gate with a concave side surface such that a portion of the concave side surface is vertically aligned with an outer surface of the first spacer; forming a word line adjacent to a first side of the first floating gate with a first distance; and forming an erase gate adjacent to a second side of the first floating gate with a second distance less than the first distance, wherein the two-step etch includes a first etch step having a first lateral etch rate and then a second etch step having a second lateral etch rate greater than the first lateral etch rate. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A semiconductor structure comprising:
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a floating gate on a semiconductor substrate, the floating gate having a concave side surface having a portion that is vertically aligned with an outer surface of a first spacer; a control gate on the floating gate; the first spacer adjacent to the control gate; a word line adjacent a first side of the first floating gate; an erase gate adjacent a second side of the floating gate, the second side being opposite the first side; a second spacer between the word line and the floating gate, the second spacer having a first thickness; and a third spacer between the floating gate and the erase gate, the third spacer having a second thickness substantially less than the first thickness. - View Dependent Claims (19, 20)
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Specification