Structure for flash memory cells

• US 8,273,625 B2
• Filed: 04/09/2010
• Issued: 09/25/2012
• Est. Priority Date: 04/09/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shen, Ming-Huei, Liu, Shih-Chang, Lo, Chi-Hsin, Tsai, Chia-Shiung, Tsao, Tsun-Kai
• Primary Examiner(s): Mandala, Michelle
• Assistant Examiner(s): Scarlett, Shaka
• Application Number:
  US12/757,172
• Publication Number:
  US 20110248328A1
• Time in Patent Office: 900 Days
• Field of Search: 257/323, 438/211
• US Class Current: 438/266
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a first floating gate on the semiconductor substrate, the floating gate having a concave side surface;

a first control gate on the first floating gate;

a first spacer adjacent to the first control gate;

a first word line adjacent a first side of the first floating gate with a first distance; and

an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side,

wherein the concave side surface has a tip portion corresponding to a widest part of the floating gate and a recessed portion corresponding to a narrowest part of the floating gate, wherein the tip portion extends to be approximately vertically aligned with an outer surface of the first spacer.

2. The semiconductor structure of claim 1 wherein the concave side surface includes a recess ratio R/T ranging between about 0.15 and about 0.25.

3. A semiconductor of claim 1 structure further comprising:

a second floating gate on the semiconductor substrate, wherein the erase gate is adjacent a first side of the second floating gate, such that the erase gate is positioned between the first and second floating gates;

a second control gate on the second floating gate; and

a second word line formed adjacent to a second side of the second floating gate, the second side of the second floating gate being opposite the first side of the second floating gate.

4. The semiconductor structure of claim 1 wherein:

the concave side surface is recessed relative to an outer surface of the first spacer.

5. The semiconductor structure of claim 1 wherein the concave side surface has a recess greater than about 20 Å

in width.

6. The semiconductor structure of claim 1 wherein portions of the first floating gate near the first control gate and the semiconductor substrate are wider relative to a middle portion of the first floating gate.

7. The semiconductor structure of claim 1 further comprising:

a second spacer positioned between the first word line and the first floating gate; and

a third spacer positioned between the first floating gate and the erase gate.

8. The semiconductor structure of claim 7 wherein the second spacer is thicker than the third spacer.

9. The semiconductor structure of claim 7 wherein the second spacer is at least 3 times thicker than the third spacer.

10. The semiconductor structure of claim 7 wherein the second spacer has a thickness of approximately 220 Å

.

11. The semiconductor structure of claim 7 wherein the first spacer has a narrow portion that has a thickness of approximately 60 Å

.

12. A method comprising:

forming a floating gate layer above a semiconductor substrate;

forming a control gate on the first floating gate;

forming a first spacer adjacent the first control gate;

etching the floating gate layer using a two-step etch to form a first floating gate with a concave side surface such that a portion of the concave side surface is vertically aligned with an outer surface of the first spacer;

forming a word line adjacent to a first side of the first floating gate with a first distance; and

forming an erase gate adjacent to a second side of the first floating gate with a second distance less than the first distance, wherein the two-step etch includes a first etch step having a first lateral etch rate and then a second etch step having a second lateral etch rate greater than the first lateral etch rate.

13. The method of claim 12 wherein the two-step etch includes the first dry etch with a first bias power and the second dry etch with a second bias power less than the first bias power.

14. The method of claim 13, wherein the first bias power is about 110 watt and the second bias power is about 45 watt.

15. The method of claim 12, wherein the two-step etch includes the first dry etch step implemented in a first etch tool having the first lateral etch rate and then the second dry etch step implemented in a second etch tool having the second lateral etch rate.

16. The method of claim 12, wherein the two-step etch uses chemicals hydrogen bromide (HBr), helium (He) and helium oxide (HeO2).

17. The method of claim 12, further comprising:

forming a second spacer between the word line and the floating gate; and

forming a third spacer between the floating gate and the erase gate;

wherein the second spacer is substantially thicker than the third spacer.

18. A semiconductor structure comprising:

a floating gate on a semiconductor substrate, the floating gate having a concave side surface having a portion that is vertically aligned with an outer surface of a first spacer;

a control gate on the floating gate;

the first spacer adjacent to the control gate;

a word line adjacent a first side of the first floating gate;

an erase gate adjacent a second side of the floating gate, the second side being opposite the first side;

a second spacer between the word line and the floating gate, the second spacer having a first thickness; and

a third spacer between the floating gate and the erase gate, the third spacer having a second thickness substantially less than the first thickness.

19. The semiconductor structure of claim 18, further comprising a word line adjacent the second spacer and an erase gate adjacent the third spacer, and

wherein the concave side surface faces the word line.

20. The semiconductor structure of claim 18, further comprising a word line adjacent the second spacer and an erase gate adjacent the third spacer, and

wherein the concave side surface faces the erase gate.