Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

• US 8,273,626 B2
• Filed: 09/29/2010
• Issued: 09/25/2012
• Est. Priority Date: 06/27/2003
• Status: Expired due to Term

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Hareland, Scott A., Chau, Robert S., Doyle, Brian S., Rios, Rafael, Linton, Tom, Datta, Suman
• Primary Examiner(s): Bryant, Kiesha
• Assistant Examiner(s): Tornow, Mark
• Application Number:
  US12/893,753
• Publication Number:
  US 20110020987A1
• Time in Patent Office: 727 Days
• Field of Search: 257347-354, 257/E21.415, 257/E21.444, 438/283, 438/284
• US Class Current: 438/283
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A method of forming a nonplanar semiconductor device comprising:

forming a semiconductor body having a top surface opposite a bottom surface and a pair of laterally opposite sidewalls above an insulating substrate;

forming a sacrificial gate electrode on the top surface and laterally opposite sidewalls, but not on any portion of the bottom surface, of a semiconductor body, the semiconductor body formed on a dielectric layer;

forming a pair of source/drain regions in said semiconductor body on opposite sides of said sacrificial gate electrode;

forming a second dielectric layer above the sacrificial gate electrode;

removing a portion of the second dielectric layer to expose the sacrificial gate electrode;

removing the sacrificial gate electrode;

removing a portion of the dielectric layer to expose an outer portion of said bottom surface, but not on an inner portion of said bottom surface, of said semiconductor body,

forming a gate dielectric on said top surface of said semiconductor body, on said laterally opposite sidewalls of said semiconductor body, and on the outer portion of said bottom surface, but not on the inner portion of said bottom surface, of said semiconductor body; and

forming a replacement gate electrode on said gate dielectric on said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body and subadjacent to said gate dielectric formed on said outer portion of said bottom surface of said semiconductor body.

2. The method of claim 1 wherein said semiconductor body is a single crystalline silicon film.

3. The method of claim 1 wherein said semiconductor body is selected from the group consisting of germanium, silicon germanium, gallium arsenide, InSb, GaP, GaSb and carbon nanotubes.

4. The method of claim 1 wherein said replacement gate electrode comprises a material selected from the group consisting of tungsten, tantalum, titanium and metal nitrides.

5. The method of claim 1 further including forming at least one additional semiconductor body having a top surface and a bottom surface, and a pair of laterally opposite sidewalls and forming a second gate dielectric layer over said top surface, said bottom surface and said sidewalls of said at least one additional semiconductor body, and wherein said gate electrode is formed on said second gate dielectric on said top surface of said at least one additional semiconductor body, and adjacent to said second gate dielectric on said laterally opposite sidewalls of said at least one additional semiconductor body, and beneath said second gate dielectric on said bottom surface of said at least one additional semiconductor body.

6. The method of claim 1, wherein the entire said top surface of said semiconductor body is planar.