Patterning methodology for uniformity control

• US 8,273,632 B2
• Filed: 10/26/2011
• Issued: 09/25/2012
• Est. Priority Date: 11/03/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yu Chao, Chang, Ming-Ching, Lin, Yih-Ann, Chen, Ryan Chia-Jen, Chen, Chao-Cheng
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US13/281,862
• Publication Number:
  US 20120108046A1
• Time in Patent Office: 335 Days
• Field of Search: 438/618, 438/700, 438/283
• US Class Current: 438/303
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a polysilicon layer over a substrate, the substrate having a topography variation;

forming a first layer over the polysilicon layer, the first layer having a thickness that substantially exceeds the topography variation of the substrate;

forming a second layer over the first layer;

patterning the second layer to form a patterned second layer that has a plurality of components separated by a plurality of openings;

patterning the first layer with the patterned second layer to form a patterned first layer; and

patterning the polysilicon layer with the patterned first layer.

2. The method of claim 1, wherein the patterning the second layer is carried out in a manner such that at least one of the components of the second layer is correlated to a critical dimension of the semiconductor device.

3. The method of claim 2, wherein the at least one of the components of the second layer has a width that is approximately equal to the critical dimension of the semiconductor device.

4. The method of claim 1, wherein the patterning the first layer includes performing an etching process in which the first layer and the second layer have substantially different etching rates.

5. The method of claim 1, wherein the thickness of the first layer exceeds the topography variation of the substrate by a factor greater than or equal to about ten.

6. The method of claim 1, further including:

after the forming the polysilicon layer and before the forming the first layer, forming a hard mask layer over the polysilicon layer, wherein the hard mask layer is formed between the polysilicon layer and the first layer.

7. The method of claim 1, wherein the patterning the polysilicon layer forms a plurality of polysilicon gates;

and further including;

after the patterning the polysilicon layer, replacing the polysilicon gates with a plurality of metal gates.

8. The method of claim 1, wherein:

the first layer contains an anti-reflective material; and

the second layer contains a dielectric material or an organic material.

9. The method of claim 1, wherein:

the first layer contains carbon and hydrogen; and

the second layer contains nitrogen.

10. A method of fabricating a semiconductor device, comprising:

forming a patternable layer over a substrate;

forming a first layer over the patternable layer;

forming a second layer over the first layer, the first and second layers having different material compositions and substantially different thicknesses;

performing a first etching process to the second layer to form a plurality of second layer components, wherein at least a subset of the second layer components each define a critical dimension of the semiconductor device;

performing a second etching process to the first layer to form a plurality of first layer components, wherein the second etching process is performed using the second layer components as etching masks; and

performing a third etching process to the patternable layer, wherein the third etching process is performed using the first layer components as etching masks.

11. The method of claim 10, wherein the substrate has a topography variation that is a fraction of the thickness of the first layer.

12. The method of claim 10, wherein the second etching process is tuned to have an etching selectivity greater than ten between the first layer and the second layer.

13. The method of claim 10, wherein the patternable layer includes a polysilicon material.

14. The method of claim 10, wherein the patternable layer includes a dielectric material.

15. The method of claim 10, wherein:

the first layer is an anti-reflective layer that contains carbon and hydrogen; and

the second layer is a dielectric layer or an organic layer.

16. A method of fabricating a semiconductor device, comprising:

forming a polysilicon layer over a substrate, the substrate having an amount of variation in topography;

forming an anti-reflective layer over the polysilicon layer, the anti-reflective layer being multiple times thicker than the amount of variation in the topography of the substrate;

forming a sacrificial layer over the anti-reflective layer, the sacrificial layer being substantially thinner than the anti-reflective layer;

patterning the sacrificial layer to form a plurality of sacrificial features, wherein at least one of the sacrificial features has a width that is a function of a critical dimension of the semiconductor device;

patterning the anti-reflective layer using the sacrificial features as masks; and

thereafter patterning the polysilicon layer using the patterned anti-reflective layer.

17. The method of claim 16, wherein:

the anti-reflective layer is at least ten times thicker than the amount of variation in the topography of the substrate; and

the width of the at least one of the sacrificial features and the critical dimension have a ratio that approaches 1;

1.

18. The method of claim 16, wherein the patterning the polysilicon layer forms a plurality of polysilicon gate components;

and further including;

replacing the polysilicon gate components with a plurality of metal gate components, respectively.

19. The method of claim 16, wherein the patterning the anti-reflective layer is carried out using a dry etching process in which the sacrificial layer and the anti-reflective layer have substantially different etching rates.

20. The method of claim 16, wherein:

the anti-reflective layer contains carbon and hydrogen; and

the sacrificial layer contains a dielectric material or an organic material.