Glass material for radio-frequency applications

• US 8,273,671 B2
• Filed: 05/23/2003
• Issued: 09/25/2012
• Est. Priority Date: 05/23/2002
• Status: Active Grant

• Current Assignee: Schott AG (Carl-Zeiss-Stiftung)
• Original Assignee: Schott AG (Carl-Zeiss-Stiftung)
• Inventors: Leib, Jürgen, Mund, Dietrich
• Primary Examiner(s): D'Aniello, Nicholas
• Application Number:
  US10/514,876
• Publication Number:
  US 20070166520A1
• Time in Patent Office: 3,413 Days
• Field of Search: 428/209, 428/426, 428/428, 428432-434, 501/55, 501/65, 501/66
• US Class Current: 501/66
• CPC Class Codes: C03B 19/00 Other methods of shaping glass manufacture or treatment of flakes, fibres or filaments from softened glass, minerals or slags C03B37/00
• CPC Class Codes: C03C 14/006 the non-glass component being in the form of microcrystallites, e.g. of optically or electrically active material
• CPC Class Codes: C03C 15/00 Surface treatment of glass, not in the form of fibres or filaments, by etching etching or surface-brightening compositions, in general C09K13/00
• CPC Class Codes: C03C 17/02 with glass C03C17/34, C03C17/44 take precedence
• CPC Class Codes: C03C 17/34 with at least two coatings having different compositions C03C17/44 takes precedence
• CPC Class Codes: C03C 2214/16 Microcrystallites, e.g. of optically or electrically active material
• CPC Class Codes: C03C 2217/21 Oxides
• CPC Class Codes: C03C 2218/15 from the vapour phase
• CPC Class Codes: C03C 2218/32 After-treatment
• CPC Class Codes: C03C 2218/328 Partly or completely removing a coating
• CPC Class Codes: C03C 2218/33 by etching
• CPC Class Codes: C03C 2218/355 Temporary coating
• CPC Class Codes: C03C 3/083 containing aluminium oxide or an iron compound
• CPC Class Codes: C03C 3/089 containing boron
• CPC Class Codes: C03C 4/12 for luminescent glass; for fluorescent glass
• CPC Class Codes: C23C 14/10 Glass or silica
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02161 the material containing more than one metal element
• CPC Class Codes: H01L 21/02263 deposition from the gas or vapour phase
• CPC Class Codes: H01L 21/31616 Deposition of Al2O3
• CPC Class Codes: H01L 21/31625 : Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
• CPC Class Codes: H01L 21/50 : Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/56 : Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2223/6627 : Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/291 : Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1903 : including wave guides
• CPC Class Codes: H01L 2924/19033 : being a coplanar line type
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01P 11/003 : Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines
• CPC Class Codes: H01P 3/003 : Coplanar lines
• CPC Class Codes: H05K 2201/0179 : Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
• CPC Class Codes: H05K 3/28 : Applying non-metallic protective coatings H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673
• CPC Class Codes: H05K 3/467 : Adding a circuit layer by thin film methods H05K3/4647 takes precedence
• CPC Class Codes: H10K 50/805 : Electrodes
• CPC Class Codes: H10K 50/8426 : Peripheral sealing arrangements, e.g. adhesives, sealants
• CPC Class Codes: H10K 50/844 : Encapsulations
• CPC Class Codes: H10K 50/846 : comprising getter material or desiccants
• CPC Class Codes: H10K 50/85 : Arrangements for extracting light from the devices
• CPC Class Codes: Y02P 40/57 : Improving the yield, e-g- reduction of reject rates
• CPC Class Codes: Y10T 428/24917 : including metal layer

Abstract

A glass material for producing insulation layers is provided. The glass material can improve the radio-frequency properties of radio-frequency substrates or radio-frequency conductor arrangements. In one embodiment, the glass material for producing insulation layers for radio-frequency substrates or radio-frequency conductor arrangements is an applied layer with a layer thickness in the range between 0.05 μm and 5″mm and has a loss factor tan δ of less than or equal to 70*10⁻⁴ in at least a frequency range above 1 GHz.

Claims

1. A process for producing a multi-layer wiring for a radio-frequency driven chip, comprising the steps of:

using the radio-frequency driven chip as a carrier and a substrate when producing the multi-layer wiring;

arranging a contact-connecting region on the substrate for electrical interconnection with the radio-frequency driven chip;

depositing a structured glass layer having a loss factor tan δ

of less than or equal to 70*10<sup>−

4</sup> in at least a frequency range above 1 GHz and at least one opening over the contact-connection region; and

applying at least one conductor structure to the structured glass layer, wherein the at least one conductor structure has electrical contact with the contact-connection region, wherein said step of depositing a structured glass layer comprises electron beam evaporation of glass material from a target that is arranged opposite and at a distance from the substrate to be coated, and wherein said step of depositing a structured glass layer comprises depositing a material having the following composition in percent by weight;

2. The process as claimed in claim 1, further comprising applying at least one passive electrical component, which is in contact with the at least one conductor structure, to the structured glass layer.

3. The process as claimed in claim 1, further comprising repeating the steps of depositing a structured glass layer and of applying at least one conductor structure a number of times.

4. The process as claimed in claim 1, wherein the step of depositing the structured glass layer comprises the steps of:

applying a structured interlayer to cover the contact-connection region;

applying the structured glass layer by evaporation coating to the substrate and the structured interlayer which is present thereon, the thickness of the structured glass layer being less than that of the structured interlayer; and

removing the structured interlayer so that regions of the structured glass layer which are located on the structured interlayer are lifted with it.

5. The process as claimed in claim 4, wherein prior to the application of the structured glass layer by evaporation coating, the method further comprises applying a conductive material that projects with respect to regions adjacent to the contact-connection region to the contact-connection region, and covering the conductive material by the structured interlayer.

6. The process as claimed in claim 4, wherein the step of applying the structured interlayer comprises printing or photolithographic structuring.

7. The process as claimed in claim 1, wherein the step of applying the at least one conductor structure comprises the steps of applying a negatively structured interlayer and depositing a conductive material.

8. The process as claimed in claim 1, wherein the at least one conductive structure is applied to the substrate prior to the step of depositing the structured glass layer.

9. The process as claimed in claim 1, further comprising the step of depositing a final glass layer and producing at least one via in the final glass layer.

10. The process as claimed in claim 1, wherein the substrate comprises a semiconductor substrate with active semiconductor regions, and wherein the step of applying the at least one conductor structure comprises connecting the at least one conductor structure to a connection location of the active semiconductor region.

11. The process as claimed in claim 1, wherein the step of applying the at least one conductor structure comprises connecting the at least one conductor structure to a via through the substrate.

12. The process as claimed in claim 1, wherein the substrate, during the application of the structured glass layer, is held at a temperature between 50°

C. and 200°

C.

13. The process as claimed in claim 1, wherein the step of depositing a structured glass layer comprises evaporation coating with a deposition rate of at least 0.1 μ

m of layer thickness per minute.

14. The process as claimed in claim 1, further comprising the step of filling in the at least one opening with a conductive material.

15. The process as claimed in claim 1, wherein the step of depositing the structured glass layer on the substrate is carried out while the substrate is joined to a wafer.

16. The process as claimed in claim 1, wherein the step of depositing the structured glass layer comprises plasma ion assisted deposition (PIAD).

17. A process for producing a multi-layer wiring for a radio-frequency driven chip on a substrate, comprising the steps of:

applying at least one conductor structure on a first side of the substrate for electrical interconnection with the radio-frequency driven chip;

defining a contact-connection region of the at least one conductor structure;

depositing an insulating glass layer, in structured form, on the first side of the substrate by electron beam evaporation coating such that the insulating glass layer has an opening at the contact-connection region;

filling the opening with a conductive material so that the conductive material is electrically connected to the at least one conductor structure; and

applying at least one further conductor structure on the insulating glass layer, the at least one further conductor structure being electrically connected to the at least one conductor structure by the conductive material, wherein the step of depositing an insulating glass layer comprises depositing a material having the following composition in percent by weight;

18. The process as claimed in claim 17, wherein the insulating glass layer has a loss factor tan δ

of less than or equal to 70*10<sup>−

4</sup> in at least a frequency range above 1 GHz.

19. The process as claimed in claim 17, wherein the step of depositing the insulating glass layer comprises evaporating a target arranged opposite and at a distance from the first side.

20. The process as claimed in claim 17, wherein the step of depositing the insulating glass layer comprises the steps of:

applying a structured interlayer to cover the contact-connection region;

applying the insulating glass layer; and

removing the structured interlayer so that a region of the insulating glass layer on the structured interlayer is lifted to define the opening.

21. A process for producing a multi-layer wiring for a radio-frequency driven chip on a substrate, comprising the steps of:

applying a first conductor structure to a first side of the substrate for electrical interconnection with the radio-frequency driven chip, the first conductor structure having a contact-connection region;

depositing, via electron beam evaporation, an insulating glass layer on the first side such that the insulating glass layer has an opening at the contact-connection region, the insulating glass layer comprises a material having the following composition in percent by weight;

SiO₂71±

5, B₂O₃26±

5, Al₂O₃1±

0.2, K₂O1±

0.2, Li₂O0.5±

0.2, and Na₂O0.5±

0.2;

filling the opening with conductive material to electrically connect the conductive material, the first conductor structure, and a second conductor structure; and

applying the second conductor structure to the insulating glass layer.

22. The process as claimed in claim 21, further comprising:

depositing, via electron beam evaporation, a second insulating glass layer covering the second conductor structure, the second insulating glass layer comprises a material having the following composition in percent by weight;

SiO₂71±

5, B₂O₃26±

5, Al₂O₃1±

0.2, K₂O1±

0.2, Li₂O0.5±

0.2, and Na₂O0.5±

0.2; and

producing at least one via in the second insulating glass layer.