Electronic logic circuit with physically unclonable function characteristics

• US 8,274,306 B1
• Filed: 03/31/2011
• Issued: 09/25/2012
• Est. Priority Date: 03/31/2011
• Status: Active Grant

• Current Assignee: United States Secretary of the Navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Garcia, Joseph P.
• Primary Examiner(s): Ismail, Shawki
• Assistant Examiner(s): Tran, Jany
• Application Number:
  US13/066,229
• Time in Patent Office: 544 Days
• Field of Search: 326 8- 15, 326 37- 41, 326/47
• US Class Current: 326/8
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H03K 19/17768 for security

Abstract

A physically unclonable function (PUF) device, with corresponding method, is provided for characterizing an integrated circuit. The PUF device includes a digital clock manager (DCM), a Butterfly circuit incorporated within the integrated circuit, and a shift register. The DCM receives a clock input signal (CLK) and imposes a temporal offset to produce a phase-shift signal (PS). The Butterfly circuit receives a first excite signal as said CLK and a second excite signal as said PS. In response, the Butterfly circuit produces an output that shifts state in response to a non-concurrent change in the CLK and PS. The shift register increments a shift count in response to the output.

Claims

1. A physically unclonable function (PUF) device for characterizing an integrated circuit, said device comprising:

a digital clock manager (DCM) that receives a clock input signal (CLK) and imposes a temporal offset to produce a phase-shift signal (PS);

a Butterfly circuit incorporated within the integrated circuit, said Butterfly circuit receiving a first excite signal as said CLK and a second excite signal as said PS to produce an output that shifts state in response to a non-concurrent change in said CLK and PS; and

a shift register to increment a shift count for said output.

2. The PUF device according to claim 1, further including:

a first latch for receiving said CLK and forwarding as said first excite signal; and

a second latch for receiving said PS and forwarding as said second excite signal.

3. The PUF device according to claim 2, further including a controller that controls said DCM and said first and second latches.

4. The PUF device according to claim 3, wherein said controller receives said shift count for a circuit database.

5. A physically unclonable function (PUF) method for characterizing an integrated circuit, said method comprising:

submitting a clock signal (CLK) to a digital clock manager (DCM) and to a first excite input of a Butterfly circuit incorporated within the integrated circuit;

imposing a temporal offset by said DCM to produce a phase-shift signal (PS);

forwarding said PS to a second excite input of said Butterfly circuit;

registering an output of said Butterfly circuit that shifts state in response to a non-concurrent change in said CLK and PS; and

incrementing a shift register in response to said output as a shift count.

6. The PUF method according to claim 5, further including:

controlling said CLK and PS via first and second latches that submit respective said first and second excite inputs to said Butterfly circuit.